Hostname: page-component-745bb68f8f-cphqk Total loading time: 0 Render date: 2025-02-11T14:58:11.011Z Has data issue: false hasContentIssue false
  • English
  • Français

Nanoscale Hafnium Oxide RRAM Devices Exhibit Pulse Dependent Behavior and Multi-level Resistance Capability

Published online by Cambridge University Press:  20 May 2016

Karsten Beckmann ,
Josh Holt ,
Harika Manem ,
Joseph Van Nostrand  and
Nathaniel C. Cady
Karsten Beckmann*
Affiliation:
SUNY Polytechnic Institute, Colleges of Nanoscale Science and Engineering, 257 Fuller Road, Albany NY 12208, U.S.A.
Josh Holt
Affiliation:
SUNY Polytechnic Institute, Colleges of Nanoscale Science and Engineering, 257 Fuller Road, Albany NY 12208, U.S.A.
Harika Manem
Affiliation:
SUNY Polytechnic Institute, Colleges of Nanoscale Science and Engineering, 257 Fuller Road, Albany NY 12208, U.S.A.
Joseph Van Nostrand
Affiliation:
Air Force Research Laboratory/RITB, 525 Brooks Rd, Rome NY 13441-4505, U.S.A.
Nathaniel C. Cady
Affiliation:
SUNY Polytechnic Institute, Colleges of Nanoscale Science and Engineering, 257 Fuller Road, Albany NY 12208, U.S.A.
*
*(Email: [email protected])
Get access

Abstract

Resistive Random Access Memory (RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance of RRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse duration. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. The RRAM devices described in this work utilize an inert tungsten bottom electrode, hafnium oxide based active switching layer, a titanium oxygen exchange layer, and an inert titanium nitride top electrode. Linear sweep and controlled pulse (down to 10 ns) based electrical characterization of RRAM devices was performed in a 1 transistor 1 RRAM (1T1R) configuration to determine endurance, reliability, retention and threshold voltage parameters. We demonstrated endurance values above 108 cycles with an average on/off ratio of 15 and pulse voltages for set/reset operation of ±1.5V. The on-chip 1T1R structures show an excellent controllability with respect to the low and high resistive state by manipulating the peak current from 75 up to 350µA we were able to achieve 10 discrete resistive states. Our results demonstrate that the set operation (which shifts the RRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage which resulted in a larger relative change of the RRAM device resistance.

Keywords

Hfmemorynanoscale
Type
Articles
Information
MRS Advances , Volume 1 , Issue 49: Electronics and Photonics , 2016 , pp. 3355 - 3360
Copyright
Copyright © Materials Research Society 2016 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

Kim, Y.-B., Lee, S. R., Lee, D., Lee, C. B., Chang, M., Hur, J. H., Lee, M.-J., Park, G.-S., Kim, C. J., Chung, U., Yoo, I.-K., and Kim, K., “Bi-layered RRAM with unlimited endurance and extremely uniform switching,” in VLSI Technology (VLSIT), 2011 Symposium on, 2011, pp. 52–53.Google Scholar
Beckmann, K., Holt, J. S., Capulong, J., Alamgir, Z., Lombardo, S., Van Nostrand, J. E., and Cady, N. C., “Endurance and Reliability of Hybrid CMOS / ReRAM for Data Storage and Encryption Applications,” 40st Annu. GOMACTech Conf., pp. 1–4, 2015.Google Scholar
Beckmann, K., Holt, J., Capulong, J., Lombardo, S., and Cady, N. C., “Reliability of fully-integrated nanoscale ReRAM / CMOS combinations as a function of on-wafer current control,” Integr. Reliab. Work. Final Rep. (IIRW), 2014 IEEE Int., pp. 159–162, 2014.Google Scholar
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., and Lu, W., “Nanoscale memristor device as synapse in neuromorphic systems.,” Nano Lett., vol. 10, no. 4, pp. 1297–301, Apr. 2010.Google Scholar
Hu, M., Li, H., Chen, Y., Wu, Q., Rose, G. S., and Linderman, R. W., “Memristor crossbar-based neuromorphic computing system: a case study.,” IEEE Trans. neural networks Learn. Syst., vol. 25, no. 10, pp. 1864–78, Oct. 2014.Google Scholar
Indiveri, G., Linares-Barranco, B., Legenstein, R., Deligeorgis, G., and Prodromakis, T., “Integration of nanoscale memristor synapses in neuromorphic computing architectures.,” Nanotechnology, vol. 24, no. 38, p. 384010, Sep. 2013.CrossRefGoogle Scholar
Manem, H., Beckmann, K., Xu, M., Carroll, R., Geer, R., and Cady, N. C., “An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors,” in 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), 2015, pp. 1–8.Google Scholar
Lee, H. Y., Chen, Y. S., Chen, P. S., Gu, P. Y., Hsu, Y. Y., Wang, S. M., Liu, W. H., Tsai, C. H., Sheu, S. S., Chiang, P. C., Lin, W. P., Lin, C. H., Chen, W. S., Chen, F. T., Lien, C. H., and Tsai, M.-J., “Evidence and solution of over-RESET problem for HfOx based resistive memory with sub-ns switching speed and high endurance,” in 2010 International Electron Devices Meeting, 2010, pp. 19.7.1–19.7.4.Google Scholar