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Maurer computers for pipelined instruction processing†
Published online by Cambridge University Press: 01 April 2008
Abstract
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new mathematical approach to the modelling of micro-architectures and the verification of their correctness and the anticipated speed-up results.
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- Copyright © Cambridge University Press 2008
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