Hostname: page-component-78c5997874-fbnjt Total loading time: 0 Render date: 2024-11-19T15:33:05.284Z Has data issue: false hasContentIssue false
  • English
  • Français

On the operating unit size of load/store architectures†

Published online by Cambridge University Press:  04 February 2010

J. A. BERGSTRA  and
C. A. MIDDELBURG
J. A. BERGSTRA
Affiliation:
Informatics Institute, University of Amsterdam, Science Park 904, 1098 XH Amsterdam, the Netherlands Email: [email protected], [email protected]
C. A. MIDDELBURG
Affiliation:
Informatics Institute, University of Amsterdam, Science Park 904, 1098 XH Amsterdam, the Netherlands Email: [email protected], [email protected]
Get access Rights & Permissions [Opens in a new window]

Abstract

We introduce a strict version of the concept of a load/store instruction set architecture in the setting of Maurer machines. We take the view that transformations on the states of a Maurer machine are achieved by applying threads as considered in thread algebra to the Maurer machine. We study how the transformations on the states of the main memory of a strict load/store instruction set architecture that can be achieved by applying threads depend on the operating unit size, the cardinality of the instruction set and the maximal number of states of the threads.

Type
Paper
Information
Mathematical Structures in Computer Science , Volume 20 , Issue 3 , June 2010 , pp. 395 - 417
Copyright
Copyright © Cambridge University Press 2010

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Baeten, J. C. M. and Weijland, W. P. (1990) Process Algebra, Cambridge Tracts in Theoretical Computer Science 18, Cambridge University Press.CrossRefGoogle Scholar
Bergstra, J. A. and Bethke, I. (2003) Polarized process algebra and program equivalence. In: Baeten, J. C. M., Lenstra, J. K., Parrow, J. and Woeginger, G. J. (eds.) Proceedings 30th ICALP. Springer-Verlag Lecture Notes in Computer Science 2719 1–21.CrossRefGoogle Scholar
Bergstra, J. A. and Loots, M. E. (2002) Program algebra for sequential code. Journal of Logic and Algebraic Programming 51 (2)125–156.CrossRefGoogle Scholar
Bergstra, J. A. and Middelburg, C. A. (2006) Thread algebra with multi-level strategies. Fundamenta Informaticae 71 (2/3)153–182.Google Scholar
Bergstra, J. A. and Middelburg, C. A. (2007) Maurer computers with single-thread control. Fundamenta Informaticae 80 (4)333–362.Google Scholar
Bergstra, J. A. and Middelburg, C. A. (2008) Maurer computers for pipelined instruction processing. Mathematical Structures in Computer Science 18 (2)373–409.CrossRefGoogle Scholar
Bergstra, J. A. and Ponse, A. (2002) Combining programs and state machines. Journal of Logic and Algebraic Programming 51 (2)175–192.CrossRefGoogle Scholar
Hennessy, J. L. and Patterson, D. A. (2003) Computer Architecture: A Quantitative Approach, third edition, Morgan Kaufmann.Google Scholar
Hoare, C. A. R. (1985) Communicating Sequential Processes, Prentice-Hall.Google Scholar
Hopcroft, J. E., Motwani, R. and Ullman, J. D. (2001) Introduction to Automata Theory, Languages and Computation, second edition, Addison-Wesley.Google Scholar
Maurer, W. D. (1966) A theory of computer instructions. Journal of the ACM 13 (2)226–235.CrossRefGoogle Scholar
Maurer, W. D. (2006) A theory of computer instructions. Science of Computer Programming 60 244–273.CrossRefGoogle Scholar
Milner, R. (1989) Communication and Concurrency, Prentice-Hall.Google Scholar
Thornton, J. (1970) Design of a Computer – The Control Data 6600, Scott, Foresman and Co.Google Scholar