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Injection Molding Simulation of 3D Stacked-Chip Assembly Packaging with Different Entrances

Published online by Cambridge University Press:  05 May 2011

C.-M. Lin ,
T.-C. Lin ,
H.-M. Chu  and
Y.-L. Chen
C.-M. Lin*
Affiliation:
Department of Mechanical Engineering, WuFeng Institute of Technology, Chia-Yi, Taiwan 62153, R.O.C.
T.-C. Lin*
Affiliation:
Department of Computer Science and Information Engineering, WuFeng Institute of Technology, Chia-Yi, Taiwan 62153, R.O.C.
H.-M. Chu*
Affiliation:
Department of Mechanical Engineering, Yung-Ta Institute of Technology and Commerce, Ping-Tung, Taiwan 90942, R.O.C.
Y.-L. Chen*
Affiliation:
Department of Fire Science, WuFeng Institute of Technology, Chia-Yi, Taiwan 62153, R.O.C.
*
*Associate Professor
**Assistant Professor
**Assistant Professor
*Associate Professor
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Abstract

This paper adopts a three-dimensional (3D) finite element method to simulate the injection molding of organic 3D stacked-chip assemblies. The geometry model of the assembly is simplified to a five-layered structure of stacked-chips with no solder bumps. The injection molding process incorporates 3D stacked-chip packaging and encapsulation techniques, and comprises primarily of multi-layer cavity-filling and reactive-thermosetting curing processes. The current investigation considers the effects of specifying different entrances on the resultant flow fronts, air-traps, and weld-lines. In general, the present results confirm the value of performing numerical simulations of the 3D stacked-chip packaging process to support the injection molding CAE approaches which are commonly applied nowadays to improve the packaging assembly design and to facilitate the rapid set up of mass-production conditions. The simulation results indicate that the best packaging results are obtained when the melt is introduced either at the center of the periphery side of the stacked-chip modulus or at its corner.

Keywords

3D stacked-chip packagingInjection moldingEncapsulationAir-trapWeld-lineThermosettingCuring.
Type
Articles
Information
Journal of Mechanics , Volume 23 , Issue 1 , March 2007 , pp. 31 - 39
Copyright
Copyright © The Society of Theoretical and Applied Mechanics, R.O.C. 2007

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References

1.Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York (1996).Google Scholar
2.Lau, J. H., Chip On Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York (1994).Google Scholar
3.Wun, W. and Lau, J. H., Circuit World, 21, pp. 25–32 (1995).Google Scholar
4.Ilyas, Mohammmed and Kim, Y.-G., “Design and Reliability of High-Density μiZ™ -Ball Stack Technology,” Proceedings of IMAPS 2002, Denver, Colorado (2002).Google Scholar
5.Elie, , Awad, , Ding, , Hanyi, , Graf, , Richard, S., and Maloney, J.J., “Stacked-Chip Packaging: Electrical, Mechanical, and Thermal Challenges,” 2004 Electronic Components and Technology Conference, pp. 1608–1613.Google Scholar
6.Yeh, M. K., Chiang, K. N. and Su, J. A., “Thermal Stress Analysis of Thermally-Enhanced Plastic Ball Grid Array Electronic Packaging,” Chinese Journal of Mechanics, Series A, Vol.18, pp. 9–16 (2002).Google Scholar
7.Powell, D. O. and Trivedi, A. K., Proc. Of43rd Electronic Components & Technology Conference, Orlando, FL, p. 182(1993).Google Scholar
8.Laroche, D., Nguyen, L. T., Boutin, L. and Bellefleur, E., “Optimization of the Transfer Molding Process in Microchip Encapsulation,” Adv. Comp.-Aided Eng. (CAE) Polymer Process., MD–49, pp. 209–223 (1994).Google Scholar
9.Turng, L. S., “Computer Aided Engineering (CAE) for the Microelectronic Packaging Process,” Adv. Comp.-Aided Eng. (CAE) Polym. Process., MD–49, pp. 191–208 (1994).Google Scholar
10.Han, S. and Wang, K. K., “Flow Analysis in a Cavity with Lead Frame During Semiconductor Chip Encapsulation,” Adv. Electron. Packag., 10–1, pp. 73–80 (1995).Google Scholar
11.Chang, R. Y., Yang, W. H., Chen, E., Lin, C. and Hsu, C. H., “On the Dynamics of Air-Trap in the Encapsulation Process of Microelectronic Package,” Proc. ANTEC ‘98 Conf. (1998).Google Scholar
12.Hieber, C. A. and Shen, S. F., “Flow Analysis of the Non-Isothermal Two-Dimensional Filling Process in Injection Molding,” Israel J. Tech., 16, pp. 248–254 (1978).Google Scholar
13.Chang, R. Y., Yang, W. H., Hwang, S. J. and Su, F., “Three-Dimensional Modeling of Mold Filling in Microelectronics Encapsulation Process,” IEEE Transactions on Components and Packaging Technologies, 27(1) pp. 200–209 (2004).CrossRefGoogle Scholar