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Surface planarity and microstructure of low temperature silicon SEG and ELO

Published online by Cambridge University Press:  31 January 2011

M.C. Arst
Affiliation:
Philips Research and Development Center, Signetics Company, 811 East Arques Avenue, Sunnyvale, California 94088–3409
K.N. Ritz
Affiliation:
Philips Research and Development Center, Signetics Company, 811 East Arques Avenue, Sunnyvale, California 94088–3409
S. Redkar
Affiliation:
Philips Research and Development Center, Signetics Company, 811 East Arques Avenue, Sunnyvale, California 94088–3409
J.O. Borland
Affiliation:
Philips Research and Development Center, Signetics Company, 811 East Arques Avenue, Sunnyvale, California 94088–3409
J. Hann
Affiliation:
Applied Materials, Inc., 3050 Bowers Avenue, Santa Clara, California 95051
J.T. Chen
Affiliation:
22409 St. Andrews Avenue, Cupertino, California 95014
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Abstract

Surface planarity and epi/SiO2 interface characteristics of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO), deposited at 800–950 °C/10 or 25 Torr, have been studied for micron-sized structures. SEG at 860 °C showed superior planarity and reduced ratio of facet width to epi thickness, compared to higher deposition temperatures. Data showed that epi/SiO2 interface defects are greatly reduced for structures parallel to (100) and/or by adding HCl to the source gas, compared to interfaces positioned at standard orientation (110) on a (100) substrate. The transition from SEG to ELO in view of the facet orientations will be discussed. To correlate structural with electrical data, n+/p diodes were fabricated on as-grown and polish planarized SEG. Leakage current values of approximately 100 nA/cm2 could be measured. These are comparable to similar n+/p junctions fabricated on conventional epi.

Type
Articles
Copyright
Copyright © Materials Research Society 1991

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References

1Voss, H-J. and Kuerten, H., IEEE/IEDM 1983 2.5, 35 (1983).Google Scholar
2Wise, R., Proceedings of the Electrochem Soc, Chem. Vapor Deposition, edited by Cullen, G. W., 253 (1987).Google Scholar
3Pagliaro, R. Jr, Corbay, J. F., Jastrzebski, L., and Soydan, R., J. Electrochem. Soc: Solid-State Science and Technology, May (1987).Google Scholar
4Regolini, J. L., Bensahel, D., Scheid, E., and Mercier, J., Appl. Phys. Lett. 54 (7), 658 (1989).CrossRefGoogle Scholar
5Borland, J., Wise, R., Oka, Y., Gangani, M., Fong, S., and Matsumoto, Y., Solid State Technology, 111 (1988).Google Scholar
6Ishitani, A., Kitajima, H., Endo, N., and Kasai, N., Jpn. J. Appl. Phys. A24 (10), 1267 (1985).CrossRefGoogle Scholar
7Ishitani, A., Kitajima, H., Tanno, K., and Tsuya, H., Microelectronic Engineering 4, 3 (1986).CrossRefGoogle Scholar
8Drowley, C. I., Reid, G. A., and Hull, R., Appl. Phys. Lett. 52 (7), 546 (1988).CrossRefGoogle Scholar
9Kitajima, H. and Ishitani, A., Electrochem. Soc, Extended Abstracts Vol. 86–1, Spring Meeting, May 49, 270 (1986).Google Scholar
10Pai, C. S., Knoell, R. V., Paulnack, C. L., and Langer, P. H., J. Electrochem. Soc. 137 (3), 971 (1990).CrossRefGoogle Scholar
11El-Diwany, M., Borland, J., Chen, J., Hu, S., Wijnen, P. v., Vorst, C., Akylas, V., Brassington, M., and Razouk, R., IEEE/IEDM 89, 245 (1989).Google Scholar