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Porosity scaling strategies for low-k films

Published online by Cambridge University Press:  25 November 2015

David J. Michalak*
Affiliation:
Components Research, Intel Corporation, Hillsboro, OR 97124, USA
James M. Blackwell
Affiliation:
Components Research, Intel Corporation, Hillsboro, OR 97124, USA
Jessica M. Torres
Affiliation:
Components Research, Intel Corporation, Hillsboro, OR 97124, USA
Arkaprabha Sengupta
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, USA
Lauren E. Kreno
Affiliation:
Components Research, Intel Corporation, Hillsboro, OR 97124, USA
James S. Clarke
Affiliation:
Components Research, Intel Corporation, Hillsboro, OR 97124, USA
Daniel Pantuso
Affiliation:
Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, USA
*
a)Address all correspondence to this author. e-mail: [email protected]
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Abstract

Reducing the delay of backend interconnects is critical in delivering improved performance in next generation computer chips. One option is to implement interlayer dielectric (ILD) materials with increasingly lower dielectric constant (k) values. Despite industry need, there has been a recent decrease in study and production of these materials in academia and business communities. We have generated a backbone and porogen system that allows us to control porosity from 0 to 60% volume, achieve k-values from 3.4 to 1.6, maintain high chemical stability to various wet cleans, and deliver uniquely high mechanical strength at a given porosity. Finite element modeling and experimental results demonstrate that further improvements can be achieved through control of the pore volume into an ordered network. With hopes to spur more materials development, this paper discusses some molecular design and nanoscale hierarchical principles relevant to making next generation low-k ILD materials.

Type
Invited Feature Papers
Copyright
Copyright © Materials Research Society 2015 

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References

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