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Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack

Published online by Cambridge University Press:  31 January 2011

A. M. Dhote
Affiliation:
Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
S. Madhukar
Affiliation:
Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
D. Young
Affiliation:
Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
T. Venkatesan
Affiliation:
Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
R. Ramesh
Affiliation:
Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
C. M. Cotell
Affiliation:
Surface Modification Branch, U.S. Naval Research Laboratory, Washington, DC 20375
Joseph M. Benedetto
Affiliation:
Army Research Laboratories, Adelphi, Maryland 20783
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Abstract

Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly-Si/Si substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500–600 °C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100 °C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.

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Articles
Copyright
Copyright © Materials Research Society 1997

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References

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