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Thermal characterization of vertical silicon nanowires

Published online by Cambridge University Press:  23 June 2011

Andrej Stranz ,
Andreas Waag  and
Erwin Peiner
Andrej Stranz
Affiliation:
Institute of Semiconductor Technology, TU Braunschweig, University of Technology, 38106 Braunschweig, Germany
Andreas Waag
Affiliation:
Institute of Semiconductor Technology, TU Braunschweig, University of Technology, 38106 Braunschweig, Germany
Erwin Peiner*
Affiliation:
Institute of Semiconductor Technology, TU Braunschweig, University of Technology, 38106 Braunschweig, Germany
*
a)Address all correspondence to this author. e-mail: [email protected]
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Abstract

Arrays of vertically aligned silicon wires of 250 nm–4 μm in diameter were fabricated in a top–down process using photolithography and deep reactive ion etching at cryogenic temperatures. Using the 3-omega method, thermal conductance of vertical silicon nanowires, i.e., nanopillars, was measured immediately on-chip without the need of breaking off single wires and mounting them into a special testing device. The Seebeck coefficient was measured with 2-mm2 arrays of pillars of 260 nm in diameter, which were pressure-joined with bulk chips for testing. Testing was performed in the temperature range between 50 and 470 °C at applied temperature gradients of up to 190 °C. We found a reduction of the thermal conductivity to less than 30% of the bulk silicon, confirming that arrayed vertical nanowires fabricated in an economical top–down process can strongly promote silicon as a thermoelectric material.

Keywords

Thermal conductivityThermoelectricNanoscale
Type
Articles
Information
Journal of Materials Research , Volume 26 , Issue 15: Focus Issue: Advances in Thermoelectric Materials , 14 August 2011 , pp. 1958 - 1962
Copyright
Copyright © Materials Research Society 2011

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