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Surface states in a monolayer MoS2 transistor

Published online by Cambridge University Press:  26 January 2016

Zhongyuan Lu ,
Oukjae Lee ,
Justin C. Wong  and
Sayeef Salahuddin
Zhongyuan Lu
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
Oukjae Lee
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
Justin C. Wong
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
Sayeef Salahuddin*
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
*
a) Address all correspondence to this author. e-mail: [email protected]
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Abstract

In this article, we have explored the interface states that form between the channel of a monolayer MoS2 transistor and a high-κ gate dielectric. These interface states lead to large hysteresis in the drain current versus gate voltage characteristic or the so-called transfer characteristic of the transistor. By applying carefully designed pulses to the gate of the transistor, we show that it is possible to both understand the nature of the interface states and minimize the hysteresis, so that the transfer characteristic can be reliably used for subsequent extraction of material parameters such as mobility.

Keywords

nanostructuremicroelectronicsthin film
Type
Invited Articles
Information
Journal of Materials Research , Volume 31 , Issue 7: Focus Issue: Two-Dimensional Heterostructure Materials , 14 April 2016 , pp. 911 - 916
Copyright
Copyright © Materials Research Society 2016 

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References

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