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The Reduceron reconfigured and re-evaluated
Published online by Cambridge University Press: 10 July 2012
Abstract
A new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.
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- Information
- Journal of Functional Programming , Volume 22 , Special Issue 4-5: ICFP 2010 , September 2012 , pp. 574 - 613
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- Copyright © Cambridge University Press 2012
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