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A multi-octave microwave 6-bit true time delay with low amplitude and delay variation in 65 nm CMOS

Published online by Cambridge University Press:  05 April 2021

Yakov Gutkin ,
Asher Madjar Open the ORCID record for Asher Madjar [Opens in a new window]  and
Emanuel Cohen
Yakov Gutkin
Affiliation:
Electrical Engineering Department, Technion – Israel Institute of Technology, Haifa, Israel
Asher Madjar*
Affiliation:
Electrical Engineering Department, Technion – Israel Institute of Technology, Haifa, Israel
Emanuel Cohen
Affiliation:
Electrical Engineering Department, Technion – Israel Institute of Technology, Haifa, Israel
*
Author for correspondence: Asher Madjar, E-mail: [email protected]
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Abstract

In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

Keywords

Monolithicphased arrayRFICtrue time delaywidebandall pass network
Type
Active Circuits
Information
International Journal of Microwave and Wireless Technologies , Volume 14 , Issue 4 , May 2022 , pp. 407 - 416
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Copyright
Copyright © The Author(s), 2021. Published by Cambridge University Press in association with the European Microwave Association

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