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Design and layout strategies for integrated frequency synthesizers with high spectral purity

Published online by Cambridge University Press:  05 June 2017

Frank Herzel  and
Dietmar Kissinger
Frank Herzel*
Affiliation:
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Dietmar Kissinger
Affiliation:
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany Technische Universität Berlin, Einsteinufer 17, 10587 Berlin, Germany
*
Corresponding author: F. Herzel Email: [email protected]
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Abstract

Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.

Keywords

Noise analysisRF front-endsFrequency synthesizer
Type
Tutorial and Review Paper
Information
International Journal of Microwave and Wireless Technologies , Volume 9 , Issue 9 , November 2017 , pp. 1791 - 1797
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2017 

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References

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