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Combined D-optimal design and generalized regression neuralnetwork for modeling of plasma etching rate

Published online by Cambridge University Press:  22 September 2014

Hailong You*
Affiliation:
School of Microelectronics, Xidian University, Xi’an 710071, P.R. China Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi’an 710071, P.R. China
Yong Chen
Affiliation:
School of Economics and Management, Xidian University, Xi’an 710071, P.R. China
Peng Liu
Affiliation:
School of Microelectronics, Xidian University, Xi’an 710071, P.R. China Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi’an 710071, P.R. China
Xinzhang Jia
Affiliation:
School of Microelectronics, Xidian University, Xi’an 710071, P.R. China Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi’an 710071, P.R. China
*
Correspondence:[email protected]
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Abstract

Plasma etching process plays a critical role in semiconductor manufacturing. Becausephysical and chemical mechanisms involved in plasma etching are extremely complicated,models supporting process control are difficult to construct. This paper uses a 35-runD-optimal design to efficiently collect data under well planned conditions for importantcontrollable variables such as power, pressure, electrode gap and gas flows ofCl2 and He andthe response, etching rate, for building an empirical underlying model. Since therelationship between the control and response variables could be highly nonlinear, ageneralized regression neural network is used to select important model variables andtheir combination effects and to fit the model. Compared with the response surfacemethodology, the proposed method has better prediction performance in training and testingsamples. A success application of the model to control the plasma etching processdemonstrates the effectiveness of the methods.

Type
Research Article
Copyright
© EDP Sciences 2014

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References

H. Ramakrishnan et al., Analysing the effect of process variation to reduce parametric yield loss, IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, ICICDT. Austin, TX, USA, 2008
Sung-Woo, P. et al., Microelectron. Eng. 66, 488495 (2003)
Hsin-Te, L., Jie-Ren, S., Y. Yung-Kuang, Int. J. Adv. Manufact. Technol. 38, 674682 (2008) Google Scholar
Z.N. Mevawalla, G.S. May, M.W. Kiehlbauch, Neural networks for advanced process control, in Advanced Semiconductor Manufacturing Conference (ASMC), IEEE/SEMI, San Francisco, CA, USA, 2010
Long, Y.H., J.X. Zhang, Chin. J. Electron. 16, 6972 (2007) Google Scholar
Byungwhan, K., Bae, J.K., W.-S. Hong, J. Vac. Sci. Technol. A 23, 355358 (2005) Google Scholar
Stokes, D., G.S. May, IEEE Trans. Semicond. Manufact. 13, 469480 (2000) CrossRefGoogle Scholar
Hong, S.J., May, G.S., P. Dong-Cheol, IEEE Trans. Semicond. Manufact. 16, 598608 (2003) Google Scholar
Byungwhan, K. et al., J. Appl. Phys. 105, 113302 (2009)
Hong, S.J., G.S. May, IEEE Trans. Semicond. Manufact. 17, 408421 (2004) CrossRefGoogle Scholar
Kim, B., Lee, D., K.H. Kwon, J. Appl. Phys. 96, 36123616 (2004) CrossRefGoogle Scholar
Kim, B., K. Park, Microelectron. Eng. 77, 150157 (2005) CrossRefGoogle Scholar
Specht, D.F., IEEE Trans. Neural Networks 2, 568576 (1991) CrossRef