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Part 1 - Formal methods and verification

Published online by Cambridge University Press:  06 November 2009

Edited by
K. McEvoy  and
J. V. Tucker
K. McEvoy
Affiliation:
University of Leeds
J. V. Tucker
Affiliation:
University of Wales, Swansea
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Summary

This part describes three different approaches to the use of formal methods in the verification and design of systems and circuits.

Chapter 2 describes the stages involved in the verification of a counter using a mechanized theorem prover.

The next chapter describes a mathematical model of synchronous computation within which formal transformations which are useful in the design process can be defined.

Chapter 4 describes verification in a different framework – that of the algebra of communicating processes.

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Chapter
Information
Theoretical Foundations of VLSI Design , pp. 63 - 64
Publisher: Cambridge University Press
Print publication year: 1990

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