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2 - FinFETs: from devices to architectures

Published online by Cambridge University Press:  05 August 2015

By
Debajit Bhattacharya  and
Niraj K. Jha
Edited by
Xicheng Jiang
Debajit Bhattacharya
Affiliation:
Princeton University, Princeton, New Jersey, USA
Niraj K. Jha
Affiliation:
Princeton University, Princeton, New Jersey, USA
Xicheng Jiang
Affiliation:
Broadcom, Irvine
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Summary

Since Moore's Law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply-scaled technology nodes and thus enable continued transistor scaling. In this chapter, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level trade-offs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

Introduction

Relentless scaling of planar MOSFETs over the past four decades has delivered ever-increasing transistor density and performance to integrated circuits (ICs). However, continuing this trend in the nanometer regime is very challenging due to the drastic increase in the subthreshold leakage current (Ioff) [1–3]. Due to the very narrow channel lengths in deeply-scaled MOSFETs, the drain potential begins to influence the electrostatics of the channel and, consequently, the gate loses adequate control over the channel. As a result, the gate is unable to shut off the channel completely in the off-mode of operation, which leads to an increased Ioff between the drain and the source. The use of thinner gate oxides and high-κ dielectric materials helps alleviate this problem by increasing the gate-channel capacitance. However, thinning of gate oxides is fundamentally limited by the deterioration in gate leakage and gate-induced drain leakage (GIDL) [4–6]. Multiple-gate field-effect transistors (MGFETs), which are an alternative to planar MOSFETs, demonstrate better screening of the drain potential from the channel due to the proximity of the additional gate(s) to the channel (i.e., higher gate-channel capacitance) [7–12]. This makes MGFETs superior to planar MOSFETs in short-channel performance metrics, such as subthreshold slope (S), drain-induced barrier lowering (DIBL), and threshold voltage (Vth) roll-off. Improvement in these metrics implies less degradation in the transistor's Vth with continued scaling, which in turn implies less degradation in Ioff.

So far, we have referred to planar MOSFETs built on bulk-Si wafers (or bulk MOSFETs) as planar MOSFETs. Fully depleted silicon-on-insulator (FDSOI) MOSFETs (planar MOSFETs built atop SOI wafers) avoid the extra leakage paths from the drain to source by getting rid of the extra substrate beneath the channel [13, 14].

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Digitally-Assisted Analog and Analog-Assisted Digital IC Design , pp. 21 - 55
Publisher: Cambridge University Press
Print publication year: 2015

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