In this chapter, we deal with synchronous circuits. We begin with a formal definition that builds on the definition of combinational circuits. This definition is syntactic, and we must prove that a circuit that satisfies this definition does what we expect it to do. But how do we define what it should do? Namely, how do we specify functionality, and how do we specify timing?

We begin with a simple form of synchronous circuits that we call the canonic form. In the canonic form, it is clear what the flip-flops do, where the output is computed, and where we compute the inputs of the flip-flops. We begin by analyzing the timing of a synchronous circuit in canonic form. We show that stability during the critical segments of the flip-flops can be achieved if the clock period is sufficiently long. We also address the painful issue of initialization. The functionality of a synchronous circuit in canonic form is specified using an abstract model called a finite state machine.

We then proceed with the timing analysis of synchronous circuits in general. We present two algorithms for timing analysis. The first algorithm, FEAS, tells us if the timing constraints of the circuit are feasible. The second algorithm, Min- −Φ, finds the minimum clock period. We also present an algorithm for simulating a synchronous circuit.

Two tasks are often associated with synchronous circuits. The first task, called analysis, is to find the finite state machine that specifies the functionality of a given synchronous circuit.