Beyond transistor scaling: alternative device structures for the terascale regime

doi:10.1017/CBO9781107337886.004

2 - Beyond transistor scaling: alternative device structures for the terascale regime

from Section I - CMOS circuits and technology limits

Published online by Cambridge University Press: 05 February 2015

Zachery A. Jacobson and

Kelin J. Kuhn

Edited by

Tsu-Jae King Liu and

Kelin Kuhn

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Zachery A. Jacobson: Affiliation:
University of California, Berkeley
Kelin J. Kuhn: Affiliation:
Intel Corporation and Cornell University
Tsu-Jae King Liu: Affiliation:
University of California, Berkeley
Kelin Kuhn: Affiliation:
Cornell University, New York

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Summary

Introduction

For more than 40 years, integrated-circuit device density has experienced exponential growth (a phenomenon known as Moore’s law [1]). As traditional CMOS transistor scaling limits are being approached, there are many technologies that are being considered to supplant or integrate with CMOS to continue scaling into the terascale (1012 devices/cm2) regime. This chapter reviews some of these future device technologies.

The scope of this chapter is confined to devices that could be direct replacements for (or complements to) to existing CMOS transistors and which are not presently mature enough for volume manufacturing (e.g., high electron mobility transistors and GaN were included, but not fully depleted silicon-on-insulator, or FinFET, devices). The use of other materials in conventional transistor structures is covered only for devices in which the basic operation of the device is vastly different than that of standard silicon-based MOS transistors (e.g., GaN-channel devices were included, but not III-V-channel MOS or germanium-channel MOS devices). Furthermore, the scope is restricted to devices based on charge transport. Although spin transport devices are of increasing interest, they would require a radical shift from the existing circuit architecture used today for CMOS technology.

Additionally, some devices were not included in this review due to other wellrecognized limitations. For example, junction gate field effect transistors (JFETs) were not included, since the primary motivation of this work is extreme scalability of devices. Similarly, although organic semiconductor devices have excellent cost scaling per unit area, their potential for miniaturization and high-performance operation is poor. Carbon-based nanoelectronic structures, such as nanotubes and graphene–nanoribbon devices, also were not included due to current concerns about their manufacturability at the terascale level of integration.

Type: Chapter
Information: CMOS and Beyond
Logic Switches for Terascale Integrated Circuits
, pp. 14 - 38

DOI: https://doi.org/10.1017/CBO9781107337886.004 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2015

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