Book contents
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- 1 Energy efficiency limits of digital circuits based on CMOS transistors
- 2 Beyond transistor scaling: alternative device structures for the terascale regime
- 3 Benchmarking alternative device structures for the terascale regime
- 4 Extending CMOS with negative capacitance
- Section II Tunneling devices
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
3 - Benchmarking alternative device structures for the terascale regime
from Section I - CMOS circuits and technology limits
Published online by Cambridge University Press: 05 February 2015
Book contents
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- 1 Energy efficiency limits of digital circuits based on CMOS transistors
- 2 Beyond transistor scaling: alternative device structures for the terascale regime
- 3 Benchmarking alternative device structures for the terascale regime
- 4 Extending CMOS with negative capacitance
- Section II Tunneling devices
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
Summary
Introduction
In this chapter, the devices discussed in Chapter 2 are benchmarked against performance targets set by the International Technology Roadmap for Semiconductors (ITRS), as well as against more conventional ultra-thin body (UTB), gate-all-around (GAA), junctionless accumulation mode (JAM) devices, and thin-film transistors.
The chapter begins with a short introduction to the scaling potential of the various devices used in the benchmarking discussion. The benchmarking metrics are then introduced, followed by the benchmarking results, discussion, and conclusions.
Scaling potential of alternative device structures
High electron mobility transistors (HEMT)
The high electron mobility transistor, or HEMT, increases device mobility by separating charge carriers from the ionized dopant atoms, thus reducing ionized impurity scattering. This is accomplished by confining carriers in an undoped quantum well.
Several groups have addressed the dimensional scaling of HEMTs [1–4]. Using electron beam lithography and multiple etch steps, Waldron et al. showed that it is possible to reduce a HEMT down to 30 nm gate-to-contact spacing, but it is difficult to make the gate length small without improvements to the etch processes [1]. Kharche et al. found that InAs is projected to scale well, as quantum well width scaling brings improvements in Ion/Ioff due to lower Ioff [2]. The reduced well width brings the electron peak closer to the gate, allowing for better gate control. Oh and Wong showed that if issues with gate leakage and process integration at small gate lengths can be solved (along with finding a symmetric p-type device), HEMT devices can have lower delay or lower energy-delay product (EDP) [3]. However, others, including Skotnicki and Boeuf, have shown that when drain-induced barrier lowering (DIBL) and sub-threshold swing (S) are included in an effective current metric, strained silicon performs better than III-V HEMTs [4].
- Type
- Chapter
- Information
- CMOS and BeyondLogic Switches for Terascale Integrated Circuits, pp. 39 - 55Publisher: Cambridge University PressPrint publication year: 2015
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