Book contents
- Frontmatter
- Contents
- Figures
- Tables
- Foreword
- Acknowledgments
- 1 Introduction
- 2 Projection-based model order reduction algorithms
- 3 Truncated balanced realization methods for MOR
- 4 Passive balanced truncation of linear systems in descriptor form
- 5 Passive hierarchical model order reduction
- 6 Terminal reduction of linear dynamic circuits
- 7 Vector-potential equivalent circuit for inductance modeling
- 8 Structure-preserving model order reduction
- 9 Block structure-preserving reduction for RLCK circuits
- 10 Model optimization and passivity enforcement
- 11 General multi-port circuit realization
- 12 Reduction for multi-terminal interconnect circuits
- 13 Passive modeling by signal waveform shaping
- References
- Index
5 - Passive hierarchical model order reduction
Published online by Cambridge University Press: 19 January 2010
- Frontmatter
- Contents
- Figures
- Tables
- Foreword
- Acknowledgments
- 1 Introduction
- 2 Projection-based model order reduction algorithms
- 3 Truncated balanced realization methods for MOR
- 4 Passive balanced truncation of linear systems in descriptor form
- 5 Passive hierarchical model order reduction
- 6 Terminal reduction of linear dynamic circuits
- 7 Vector-potential equivalent circuit for inductance modeling
- 8 Structure-preserving model order reduction
- 9 Block structure-preserving reduction for RLCK circuits
- 10 Model optimization and passivity enforcement
- 11 General multi-port circuit realization
- 12 Reduction for multi-terminal interconnect circuits
- 13 Passive modeling by signal waveform shaping
- References
- Index
Summary
In this chapter, we focus on passive wideband modeling of RLCM circuits. We propose a new passive wideband reduction and realization framework for general passive high-order RLCM circuits. Our method starts with large RLCM circuits, which are extracted by existing geometry extraction tools like FastCap [83] and FastHenry [59] under some relaxation conditions of the full-wave Maxwell equations (like electro-quasi-static for FastCap or magneto-quasi-static for FastHenry) instead of measured or simulated data. It is our ultimate goal that we can obtain the compact models directly from complex interconnect geometry without measurement or full-wave simulations. The method presented in this chapter is called hierarchical model order reduction, HMOR, which is based on the general frequency-domain hierarchical model reduction algorithm [121, 122, 124] and an improved VPEC (vector potential equivalent circuit) [134] model for self and mutual inductance, which can be easily sparsified and is hierarchical-reduction friendly.
The HMOR method achieves passive wideband modeling of RLC circuits via multi-point expension and the convex programming based passivity enforcement method. In this section, we will show that the frequency-domain hierarchical reduction is equivalent to implicit moment-matching around s = 0, and that the existing hierarchical reduction method by one-point expansion [121, 124] is numerically stable for general tree-structured circuits.
- Type
- Chapter
- Information
- Advanced Model Order Reduction Techniques in VLSI Design , pp. 67 - 92Publisher: Cambridge University PressPrint publication year: 2007