Reliability issues have assumed greater importance as critical dimensions in microelectronic devices have entered the sub-micron regime. Wafer level reliability tests have been performed to study the breakdown energy of aluminum. 1500Å, 3500Å, 5500Å and 7500A aluminum films were sputter deposited at 400°C on oxideon-silicon substrates. Test structures with line widths varying from 1 μm to 10 μm were defined on the metal film. The aluminum lines were then passivated using a stacked layer of silicon dioxide and silicon nitride. Finally, the substrates were alloyed at temperatures from 400°C to 450°C. An attempt has been made to minimize process variability effects by processing the substrates through the same process conditions as far as possible. Failure was induced by stressing the metal lines with high DC current densities and at a constant slew rate. The samples were characterized using optical and scanning electron microscopy. Failure analysis of the samples processed under the different conditions will be discussed.

Mass transport by electromigration in sputtered Cu line segments on a continuous W line has been measured using the drift velocity technique at temperatures from 166 to 396 °C. The Ta/Cu/Ta line segments are patterned by dry etching techniques. Cu mass depletion (voids) at the cathode end and accumulation (hillocks) at the anode were measured as a function of time from scanning electron microscope micrographs. The edge displacement of Cu was found to increase linearly with time. The activation energy for Cu electromigration drift velocity, which relates to the product of effective charge number and diffusivity, Z*D, is found to be 0.6 eV.

Traditional electromigration life testing is a time-consuming and often painful process, consuming many expensive samples and weeks of valuable time to collect enough data for a statistically significant conclusion. Annoying, to say the least, this often causes real problems in process development when cycle times of new products can often be measured in months. Therefore, there has been a strong incentive to search for alternatives.

Electroless deposition of planarized copper in SiO2 trenches has been carried out using Pd/Si plasma immersion ion implantation (PIII) or Pd2Si deposition to form a seed layer at the bottom of trenches. Electrical resistivity of the plated Cu is ≤ 2 μΩ-c-m for both types of seeding layers. For the PIII seeding method, we found a threshold Pd dose of 2 ×1014/cm2 is required to initiate Cu plating, and RBS analysis confirms intermixing of Pd, Si, and SiO2 improves the adhesion of the plated Cu to SiO2. Electromigration tests show both void and hillock formation under accelerated current stress testing, with an activation energy of 0.8 eV for interconnect open failure. The DC and pulse-DC median-time-to-failure (MTF) of plated Cu are found to be about two orders of magnitude longer than that of AI-2%Si at 275°C, and about four orders of magnitude longer than that of AI-2%Si when extrapolated to room temperature. Pulsed DC electromigration stressing exhibits a transition from low to high frequency behavior around 900 kHz, indicating a vacancy relaxation time much shorter than that of Al. For bipolar AC stressing, the ratio MTFAc / MTFDC of Cu is much smaller than that of A1–2%Si, indicating a different void recovery mechanism for Cu.

Ion implantation of boron and aluminium is used to passivate copper surfaces. Such a process modifies the copper only near its surface without affecting copper's desirable bulk properties. The present experiments show that implant doses as low as 1015 ions/cm2 of either boron or aluminium can reduce the oxidization rate by one order of magnitude or more compared to non-implanted samples.

Co-evaporated Cu-Ti films on thermally-oxidized Si substrates were annealed in vacuum at temperatures between 300 and 700° C. Reactions within the films and between film and substrate were monitored by Rutherford backscattering spectrometry, X-ray diffraction, transmission electron microscopy and sheet resistance. We found that, despite the competition from intermetallic compound formation, the Cu-Ti films react with SiO2 beginning at 400°C, with Ti migrating to the SiO2 interface to form both a silicide, Ti5Si3, and an oxide and to the free surface to form additional oxide. The reaction leaves relatively pristine Cu. Above 600°C, however, Cu begins to react with the underlying silicide. By comparison, pure Ti reacts with SiO2 only above ˜700°C.

The effect of a TiW capping layer on the mecheanical behavior of AlSi(1%)Cu(½%) thin films was evaluated. The aluminum films studied were deposited at temperatures ranging from 150 to 450°C, on various barrier layers (Ti, TiW, and TiN). Measurement of the stacks stress during anneal up to 450°C revealed that for films deposited at 150°C, the capping layer improved yield strength regardless of the type of barrier layer used. The uncapped stacks exhibited the traditional behavior of hillock formation during heating, and hillock/grain collapse during cooling. The capped stacks, however, showed considerably reduced, or suppressed hillock formation during heating, and active tensile stress relief mechanisms during cooling included cracking, voiding, mad grain boundary grooving. These observations correlated well with XRD data characterizing the extent of tensile stress buildup in the aluminum films. For films deposited at 300°C, grain deformation during cooling after deposition presumably caused hardening which prevented cracking as well as changes in texture during anneal. This was observed regardless of the presence of a capping layer. Although the stacks studied were unpassivated, this data suggests that capping layers may enhance stress migration issues in integrated systems.

We report hardness and Young's modulus measurements on various dielectric thin films. Hardness and modulus information was derived from indentation experiments with a Berkovich triangular-based diamond indenter in an ultra micro-indentation instrument (UMIS). We studied the effect of moisture content and phosphorous doping on hardness and Young's modulus of low temperature Chemical Vapor Deposition (CVD) Si-oxides and found that dehydration and densification tend to harden samples, whereas increased P-doping results in a lower hardness. Hardness values of silicon nitride, silicon oxynitride, sputtered oxide, spin-on-glass and APCVD Si-oxides are compared. We also discuss how deposition conditions and chemical compositions correlate to dielectric properties such as stress as well as moisture uptake, thermal expansion coefficients and hardness and modulus values. Using these results, thermal stresses in encapsulated Al lines have been calculated and the calculated stress in Al is higher when encapsulated with dielectric films with higher moduli.

A new, physically-based model has been developed to successfully explain the roles of device structure and plasma nonuniformity on charge damage. The model includes an equivalent circuit for the charging of MOS antenna structures exposed to a nonuniform plasma, and the use of SPICE, a circuit simulator, to correlate plasma measurement to breakdown measurements. The model is applied to analyze thin oxide damage in an O2 magnetron plasma asher. The simulation results show good agreement with experimental damage data of “antenna” capacitors using ramp voltage breakdown measurements.

In this paper, submicron nMOSFET's with thin LPCVD gate oxides deposited using chemical reaction of dichlorosilane and nitrous oxide at 800 °C were evaluated. Fowler-Nordheim injection was performed to compare the resistance to electron trapping and interface-state generation of these LPCVD oxides to that of the thermally grown oxides at 850 °C. It was found that with an 850 °C 20-minute post-deposition nitrogen anneal, the LPCVD oxides exhibit comparable immunity to electron trapping as the thermal oxides. Transistor characteristics such as Δgm/gm, ΔID/ID revealed to be similar for both oxides, but there was an order of magnitude higher ΔVt detected for the LPCVD oxide films (with/without anneal) than the thermal oxides. The mechanism responsible for the hot-carrier induced device degradation was also characterized in this study. It was found that the major source of hot-carrier damage was electron trapping for the thermal oxides and the N2 - annealed LPCVD oxides; while for the as-deposited LPCVD oxides, both electron trapping and interface-state generation contributed to device degradation.

The influence of 0–1000 mJ/cm2 1–2 keV x-ray radiation on the MOSFET characteristics of submicron CMOS devices is investigated. Fully-integrated LOCOS- and STI-defined MOSFET structures, with abrupt- and LDD-junction geometries, are used to evaluate irradiation effects on different device design features for future (post-256 Mb DRAM) logic and DRAM technology considerations. The effects of x-ray irradiation on DRAM trench storage-node leakage are also investigated and compared to high energy ion implant-related leakage behavior.

Electric fields with different intensities and polarities in the range corresponding to the Fowler-Nordheim (FN) tunneling injections were applied on the MOS structures to examine the generation behaviors of the positive oxide charges. The concentration changes of the field-induced positive oxide charges with the injected electron numbers were measured and a linear relation between the saturated density of the positive oxide charge and the average intensity of the oxide electric field was obtained. The experimental results show that the amount of the field-induced positive oxide charge only depends on the intensity but not on the polarity of the oxide electric field. There was a threshold value of the average oxide electric field below which no positive charge could be generated; and this implies that the generation mechanism of the positive oxide charge due to high electric field can be different from that due to low electric field.

Non-stoichiometric films are particularly attractive for non-volatile memory applications. In this work low-pressure chemical vapor deposition (LPCVD) using silane and nitrous oxide gases were used to deposit thin silicon-rich SiO2 films. Reliability issues concerning these nonstoichiometric oxides have been studied in comparison to ultrathin conventional thermal oxides. It has been found that with an increase in the silicon content, the current injection efficiency at a given electric field increases. This has significant advantage in terms of low programming voltage applications. There is also a considerable reduction in electron trapping, extremely large increase in charge-to-breakdown and negligible interface state generation in comparison to ultrathin thermal oxides. These characteristics of non-stoichiometric oxide films can be explained by a modified conduction mechanism which in turn is due to dispersed crystallites in the oxide film.

One of the major problems associated with thin dielectrics is defects in the form of micropores or voids in ultrathin SiO2 when oxides are thermally grown from the silicon substrate. This study describes the synthesis of thin multilayer stacked oxides by the sequential growth of thermal oxide layer and the deposition of a layer of LPCVD oxide followed by a densification/reoxidation step (3-step process) to reduce the density of these micropores. The electrical characteristics of these stacked oxides were compared with those of conventional thermal oxide and reoxidized-deposited oxide (2-step process). The stacked oxides formed by the 3-step process exhibit a drastic reduction of the defect density. This improvement is believed to be due to the misalignment and filling up of the micropores in the thermal oxide layer by the deposited oxide layer. Variation of the thickness of the deposited oxide shows that LPCVD oxide of about 30Å in the 3-step process is sufficient in reducing defect density and improving the breakdown characteristics of the stacked oxide. Using this simple stacked oxide process, the yield of ultrathin oxides can be improved significantly.

A new material for permanent electrostatic discharge (ESD) and corrosion protection has been developed. This material, called Reactive Polymer, consists of a blend of polymer resin (eg. polyethylene, polypropylene, ABS, PVC) with stable solid-state additives. It can be formed into bags, tubing, sheets, bubble-pack, foam, trays, IC carriers, tape-and-reel, etc. ESD and corrosion protection is provided for components, circuit packs, assembled systems, etc. Protection from corrosion or tarnish by atmospheric H2S, COS, and HCI is provided for many forms of silver, copper, and copper alloys such as the stock metals, electrical connectors, bus bars for electric power transmission, and electroplated metals.

This paper discusses the nonhermetic performance of polymer thin film coatings derived from 1,3-bis(2-bicyclo[4.2.0]octa-1,3,5-trien-3-ylethenyl)-1,1,3,3-tetramethyl disiloxane (mixed isomers, CAS 117732-87-3), known also as divinyl siloxane bis-benzocyclobutene or DVS bis-BCB. The stability of the dielectric constant and the mechanical properties have been examined before and during high temperature exposures of the polymer films to air for extended periods of time at high and low humidity. Infrared absorbance spectra and dielectric constant measurements have been correlated.

Formulations of the DVS bis-BCB prepolymer with a polymeric oxidation inhibitor are predicted to yield polymer films which display less than a 10% change in the dielectric constant after 40 years in air at 85°C. These films have excellent potential for use as the dielectric coating layer in nonhermetic packaging applications for Multi Chip Module (MCM) circuits.

Imaging is an integral part of VLSI technology development and quality control in device manufacturing. We report a novel application of Atomic Force Microscopy to image VLSI cross sections of metallographically polished samples. The major advantage of this technique over conventional imaging techniques, such as Scanning or Transmission Electron Microscopy, is the higher resolution achievable in combination with higher throughput and an easy access to quantitative data, such as line widths or re-entrant angles. We observe a very good correlation of AFM VLSI cross section images, acquired in air, with those acquired by SEM and TEM.

The correct evaluation of the test temperature is an extremely important task when performing electromigration (EM) experiments on metal lines. In fact, reliable values of activation energy for the EM mechanism can be obtained from experimental data if and only if the true value of the temperature of each test structure during the tests is known. On the other hand true temperature measurements involve more than one practical and theoretical difficulties, ranging from heating due to Joule effect to bad thermal coupling between the test devices and the temperature sensors.

In this work a method is presented for true temperature evaluation of the test stripes during electromigration median-time-to-failure tests performed at the wafer level. In particular the problem of the thermal coupling between two or more samples tested at the same time is examined.

The experimental setup for simultaneous wafer-level testing of more than one stripe, requiring a probe-card and a switching matrix, is described, along with the development of a procedure for the calculation of the true temperature of each stripe, which takes into account Joule self-heating and mutual heating of the samples.

Results obtained on Al-Si and Al-Si/TiN/Ti metallizations are shown and design guidelines to avoid thermal coupling of the samples, thus allowing more reliable temperature measurements, are provided.

This paper presents the results of a systematic TEM investigation to understand the chemical, morphological and microstructural makeup of photoresist residues following oxygen plasma ashing. The investigation was carried out on generic non-product control wafers and product wafers with a view to help aid in the identification of a suitable post-ashing cleaning process. Specimens in planview were prepared by mechanical grinding and Argon ion milling from the substrate end of the sample. Energy Dispersive X-ray Spectrometry (EDS) was used to obtain the composition and selected area electron diffraction (SAD) was used to obtain information on crystallinity. The residues were essentially amorphous and were found to be arsenic-rich in composition and exhibited a dropletlike morphology decorating areas where the photoresist was used as an implantation mask. In addition, hexagonally shaped crystals and spherical particulates of varying dimensions were seen in several regions and were found to be carbon rich.

The surfaces of various materials are often exposed to such environments as thermal cycling or irradiation. The failure processes caused by microcrackings in such an environment are studied by means of computer simulations. Crack growth is modeled as a series of processes of storage, release, and transfer of strain energies in the cubic lattice system. Surface crack pattern, crack penetration, and strain energy distribution are investigated for systems in different situations. The simulations reveal some correlations between crack pattern, crack penetration, and strain energy distribution. The results have some implications on the failure processes of materials in a thermal or radiational environment. The reliability of materials is discussed on the basis of the results of simulations.