High dielectric constant thin films for packaging applications were studied. Compared with polycrystalline or epitaxial ferroelectric thin films amorphous ferroelectric films are a promising alternative because of their ease of processing and low leakage current. Reactive Partially Ionized Beam deposition (RPIB) offers a new approach to deposit high dielectric constant films at a low substrate temperature. As an example, the growth of amorphous BaTiOs thin films using RPIB deposition is described. The films were characterized in terms of dielectric constant and leakage current. The annealing effects on the film properties are also discussed.

Thin-film reaction with solder and its influence on stress have been investigated in Cr/Co/Au and Cr/Co/Au/Pb(Sn) structures. Results from X-ray analysis and RBS measurements reveal that without the Pb(Sn) layer the dominant reaction occurs by interdiffusion of Co and Cr followed by the reaction of Cr and Au. In contrast, the addition of the Pb(Sn) layer leads to a rapid dissolution of Au into Pb, which is followed by subsequent reaction of Co and Sn. In this reaction the intermetallic phases CoSn and CoSn2 are formed. These material reactions are correlated with measurements of the mechanical stresses of the multilayer structure during annealing which were carried out using a bending beam method. The overall reaction scheme of the multilayer structure and the individual reaction kinetics are discussed.

Several industrial facilities produce electroless copper for use in printed circuit boards. One major class is the high- strength copper, so called because of its extremely high strength. During the deposition process, hydrogen is commonly incorporated into the film and it is thought to be the cause of poor ductility.

In this work, the hydrogen content was measured by the fusion technique in three sets of high strength electroless copper specimens, respectively annealed at 423, 520 and 573 K. The hydrogen content decreased very rapidly at the two higher temperatures, and tended to a saturation value of approximately 20 ppm by weight with increasing annealing time. The cavity evolution with annealing time at 520 and 573 K was studied by transmission electron microscopy (TEM). It was found that the number of cavities increased with annealing time and with increasing temperature.

The data indicate that hydrogen degassing is not controlled by bulk diffusion and, hence, that hydrogen must be trapped. A comparison with recrystallization results demonstrates that more than half of the hydrogen retained in the electroless copper is in saturable traps. The TEM observations indicate that cavity coarsening takes place during annealing at 520 and 573 K.

Tungsten fibers were fabricated with dimensions relevant to microelectronics and microfabrication. The strength and modulus were 1.57±0.7GPa and 276±lO%GPa, respectively. The failure mode was most consistent with intergranular fracture.

A novel low temperature CVD process - atom reaction CVD process for metal film depositions has been developed by using hydrogen atoms reacting with metal compounds. High purity copper films, with low resistivity of ∼ 2 μΩ cm, good step coverage to submicron holes and good adhesion to various substrates, were obtained by using this process with Cu(HFA)2 source at substrate temperatures below 150 °C.

Increases in cross-talk disturbance, signal delay and current density have a significant impact on the performance of integrated systems as the metal pitch continues to be scaled down. A metal, such as copper, which has high conductivity and high resistance to migration, will greatly alleviate these problems. A selective technique for the deposition of copper, such as electroless plating, is highly desirable because it circumvents the potential problem of dry etching copper and inherently planarizes the surface topography.

The effect of sputtering conditions of Al alloy films on the ability to fill submicron contact/vias by laser planarization has been investigated. A significant improvement in the process window (complete contact filling to optical ablation) has been observed by using high temperature and/or bias sputtering. In general, the process window increased with the increasing deposition temperature and substrate bias voltage. For 0.9 μm diameter contacts of aspect ratio ∼ 1, the process window for contact filling by AlSi(l%)Cu(0.5%) increased from 5% for standard deposition parameters to a record high 30% by using the optimized sputtering conditions.

A very flexible maskless technique for thin film hybrid formation has been developed. Lay outs are transferred directly from work stations to laser controls. Openings in ceramic substrates are achieved through laser cutting, and chips are embedded to give a common chip-to-substrate surface, flat to within 2 μm. Dielectric layers of polyimide are formed by spin on techniques and are then laser structured for via hole formation.

Interconnections of the embedded chips are generated by laser direct writing of thin copper lines from copper formate, followed by chemical copper deposition. Chemical pretreatments of the aluminum contact pads allow for reasonable chip contacting with these methods. Electrical measurements on the dc line conductivity and the high frequency behaviour of these interconnections have also been performed.

A novel method has been developed for producing customized copper interconnections on thermally-sensitive substrates by laser seeding followed by constrictioninduced electroplating. A polyimide, polytetrafluoroethylene, or glass-epoxy substrate is first sprayed with palladium acetate solution. 500 nm thick palladium interconnects are then formed using a 514 nm argon ion laser (10 mW - 50 mW) to selectively pyrolyze the acetate film. After cleaning, the part is immersed in an acid copper electrolyte and an alternating current (0.1 Amp - 2.0 Amp) passed through the palladium seed. Joule heating produces a cathodic shift in the equilibrium potential (dε0/dT = 0.63 mV/degree) which causes electrodeposition of copper along the seeded connection.

Cross-sectional microscopy and electrochemical polarization studies show that local plating current densities of 10 mA/cm2 produce 1000 εm × 25 εm × 10 εm line geometries exhibiting excellent mechanical and electrical properties. The large process window suggests that customization and repair on lincwidths below 1 mil (25 εm) should be achievable routinely.

Thin, narrow, lines were reactive ion etched from a highly textured aluminum film deposited on (100) silicon substrates; some arrays of lines were covered with a passivation layer of silicon nitride. Passivated and unpassivated lines were heat treated at 400°C.

Voids were present in nitride covered lines which were aged for over three months at room temperature as well as in nitride covered lines examined immediately after heat treatment. Voids were not visible in bare, heat treated lines. Void nucleation occurred at the points of intersection of grain boundaries with line edges and growth appeared to follow grain boundaries.

The effect of deposition pressure and controlled oxygen dosing on the diffusion barrier performance of thin film Ta to Cu penetration was investigated. In-situ resistivity, Auger compositional profiling, scanning electron microscopy and cross-sectional transmission electron microscopy were used to determine the electrical, chemical and structural changes that occur in Cu/Ta bilayers on Si upon heating. A 20 nm Ta barrier allowed the penetration of Cu at temperatures ranging from 320 to 630°C depending on processing conditions. Barrier failure temperature is dependent upon the deposition pressure and oxygen contamination at the Ta/Cu interface. This indicates the importance of understanding how deposition conditions affect diffusion barrier performance.

The application of a damage integral approach which provides numerical accounting of the accumulated fatigue damage in solder joint is reviewed. The instantaneous fatigue damage rate is determined by the solder stress state, temperature and environment using a phenomenological crack growth law. The stress is calculated using state variable constitutive relations for inelastic deformation. The material parameters for the crack growth law are determined from isothermal fatigue data. Representative damage integral calculations are used to illustrate the application of the approach. Finally, the significance of failure criteria on the apparent fatigue life is discussed in terms of the damage integral approach.

The approach developed is based on the assumption that thermal fatigue crack propagation in solder joints is primarily controlled by C* and J integrals. The effect of microstructural coarsening on crack propagation is discussed. A fracture criterion, J≥Jc, is used to define the failure of the joints. A crack growth governing equation has been formulated and can be numerically integrated to obtain the crack growth history given stress history as an input. The approach was applied to model the experiment by Wong and Helling [15]. In their experiment, surface-mounted electronic devices using eutectic Pb/Sn solder were tested in thermal cycles of −20 to 100°C and −55 to 125°C. A unified constitutive equation was assumed for the eutectic Pb/Sn solder. An equation for solving the shear stress in the joint was formulated and is coupled with the crack growth equation. Both equations were solved simultaneously by the Runge-Kutta method for the stress-time and crack growth history. The results of the prediction are in a good agreement with the experimental data, which indicates that fracture mechanics may be applied to describe the failure process of solder joints under cyclic thermal loadings.

The matrix creep failure indicator developed by Shine and Fox is extended to cases when strain is multiaxial and varies with position in the structure. Analysis of a thermal fatigue test of leaded surface mount devices found in the literature illustrates application of the method. A butt joint surface mount configuration is then tested in simple mechanical loading and also analyzed using the finite element method. It is found that the matrix creep “damage integral” method gives good correlation with observed solder fatigue failures for both cases.

The lifetime of non-compliant eutectic solder joints was improved by an order magnitude by rapid quenching. The quenching produces a fine equiaxed superplastic grain structure which lowers the stresses in the solder joints for the fatigue cycle strain range. Similarly, compliant J Bend and Gull wing joints, which last thousands of cycles, operate at lower stresses where superplastic deformation predominates.

Long term reliability of flip-chip bump bonding for application in infrared detector interconnection is investigated. The effectiveness of a thin film nickel as diffusion barrier for reducing indium-gold intermetallic formation is studied by accelerated life test and destructive physical analysis. A new interconnect structure replacing the conventional bump-to-bump configuration is described.

The mechanical properties of the solder joints, in a thin film multichip module, were evaluated using constant deformation-rate, creep and load-relaxation tests in shear mode on specially fabricated samples which are representative of the multichip configuration. While majority of the testing was performed at ambient temperature, a limited amount of study was made to characterize the temperature dependence of the deformation characteristics. Constitutive equations were developed for predicting the deformation behaviors of the solder joints under varied test conditions as well as the in-service reliability of these joints.