As computer chip technologies evolve from aluminum-based metallization schemes to their copper-based counterparts, Electrochemical Deposition (ECD) is emerging as a viable deposition technique for copper (Cu) interconnects. This paper presents the results of a first-pass study to examine the underlying mechanisms that control ECD Cu nucleation, growth kinetics, and post-deposition microstructure evolution (self-annealing), leading to the development and optimization of an ECD Cu process recipe for sub-quarter-micron device generations. The influence of bath composition, current waveform, type and texture of Cu seed layer, and device feature size (scaling effect) on the evolution of film texture, morphology, electrical properties, and fill characteristics was investigated using a manufacturing-worthy ReynoldsTech 8” wafer plating tool. Resulting films were analyzed by X-ray Diffraction (XRD), four-point resistivity probe, Focused-Ion-Beam Scanning Electron Microscopy (FIB-SEM), and Atomic Force Microscopy (AFM). These investigations identified an optimized process window for the complete fill of aggressive device structures with pure Cu with resistivity ∼ 2.0 µΩ-cm and smooth surface morphology.

Self-annealing properties of electroplated and sputtered copper films at room temperature were investigated in this study, in particular, the effect of copper film thickness, electrolyte systems used, as well as their level of organic additives for electroplating. Real-time grain growth was observed by transmission electron microscopy. Sheet resistance and X-ray diffraction measurements further confirmed the recrystallization of the electroplated copper film with time. The recrystallization of electroplated films was then compared with that of sputtered copper films.

The effect of various barrier materials on the microstructure of electroplated Copper films was investigated. Analysis of the Cu was performed at the as-deposited, room temperature stabilized, and annealed states. It shows that the barrier material can have a dramatic effect on the properties of electroplated Cu.

Transformations in electroplated Cu films from a fine to course grain crystal structure (average grain sizes went from ∼0.1 µm to several microns) were observed to strongly depend on film thickness and geometry. Thinner films underwent much slower transformations than thicker ones. A model is proposed which explains the difference in transformation rates in terms of the physical constraint experienced by the film since grain growth in thinner films is limited by film thickness. Geometrical constraints imposed by trench and via structures appear to have an even greater retardation effect on the grain growth. Experimental observations indicate that it takes much longer for Cu in damascene structures to go through grain size transformations than blanket films.

In this paper, a simple and improved method for Al via fill is demonstrated. The ALPS (Aluminum Low Pressure Seed) technique was used to deposit a smooth, highly conformal Al seed layer over an all-IMP (ionized metal plasma) Ti/TiN/Ti stack. Subsequent warm Al deposition was carried out in a conventional warm Al chamber. The ALPS method was compared to standard hot Al deposition. Physical SEM characterization and electrical data showed lower via resistances, with better yield for ALPS. No voiding was observed even within unlanded vias. With the ALPS seed layer, the IMP Ti/TiN/Ti liner stack provided a superior wetting surface compared to an IMP Ti-only liner which resulted in voids within unlanded vias. Electrical data obtained for ALPS- and hot Al-deposited Kelvin vias and via chains with various via/metal underlaps were compared with conventional CVD W plugs (using IMP TiN as the glue layer). Both Al fill methods gave lower via resistance compared with W plugs, as expected.

HDP-FSG has been integrated as an inter-metal dielectric in a multilevel interconnect scheme. Process regimes for obtaining stable HDP-FSG films were identified. Gap-fill of high aspect ratio structures was achieved for 0.18µm technology node. HDP-FSG film stability, homogeneity, and impurity content were evaluated. In addition to the development of the HDP-FSG process, integration of the interconnect module was investigated and optimized. Analysis of the AI/FSG interface integrity was tested for gap-fill and corrosion with SEM and for fluorine diffusion with SIMS. CMP rate of the FSG was determined and compared to HDP-USG. Al metallization integration approaches in conjunction with FSG were identified.

Corrosion of the titanium glue layer in a Ti/TiN/Al(Cu) /TiN ARC metal stack is observed during post metal etching polymer stripping in an alkaline chemical stripper. This novel corrosion only occurs when the underlying tungsten via plug is exposed, and leads to high resistance in vias. Investigation of the mechanism is attempted through variation of the polymer stripping duration, the deposition of the titanium and the polymer stripper, and the nitridization of the titanium layer. The high via resistance effect is solved by using analternate polymer stripper which is considered to be an inactive electrolyte for the galvanic reaction between the titanium glue layer and the exposed tungsten via.

The correlation between microstructures of Al and W metal thin films and their respective CMP performance is investigated. It is found that CMP removal rate decreases with increasing grain size. In both cases, the textures of the metal films are altered and their resistivity increased after CMP. The phenomenon is more pronounced for polish under a greater down force. The table speed, on the other hand, has only minimum effects on microstructure and resistivity. The possible underlying mechanisms leading to this phenomenon are proposed and their potential impacts on metallization reliability is discussed.

The effectiveness of a TiN capping layer to prevent the conversion of α-titantium to titanium nitride when annealed in a nitrogen ambient has been studied over the temperature range 300–700°C using in-situ high temperature diffraction and transmission electron microscopy. Over the time range of interest (four hours), no evidence of Ti reaction was observed at 300°C. At 450°C. nitrogen was found to diffuse into the Ti to form a Ti(N) solid solution. Above 500°C the titanium is transformed to a second phase: however this reaction follows two different kinetic paths, depending on the annealing temperature. Below 600°C. the reaction proceeds in two stages, with the first stage consisting of Ti(N) formation, and the second stage consisting of the conversion of the Ti(N) with a transformation mechanism characteristic of short range diffusion (grain edge nucleation). Above 600°C, a simple linear transformation rate is observed.

The precipitate formation occurring in Al-Cu thin foils with copper concentrations of either 1.15 at.% or 0.3 at.%, has been studied. In-situ X-ray diffraction analysis and differential scanning calorimetry are applied to determine the phases formed and the enthalpy changes in the same samples. Both X-ray diffraction and differential scanning calorimetry indicate that the precipitation behaviour of thin films (about 500 nm thickness) differs significantly from that of bulk material. In the films studied the precipitation of Al2Cu occurs at a much lower temperature than expected on the basis of the (bulk) phase diagram. Moreover, no intermediate phases are observed prior to Al2Cu precipitation. Also the amount of Cu in solid solution (0.20 at%Cu) observed by electron-probe micro-analysis after slowly cooling from 500°C to room temperature, exceeds the solubility of bulk Al-Cu.

This paper reports on the influence of the copper concentration on the mechanical behaviour during thermal cycling and during isothermal holds of Al-Cu thin films on Si substrates. The Cu concentration has been varied in the range between 0 to 1 at.%

Upon heating, the films with the larger amount of Cu showed a clear maximum in compressive stress. Moreover, during cooling these samples show a tensile stress increase at the onset precipitation temperature. Further cooling below 200 °C leads to the characteristic tensile stress increase often observed for Al-Cu thin films. An isothermal hold during cooling at 250 °C leads to temporary strengthening of all Al-Cu. The extent of the strengthening is dependent on the Cu concentration and is clearly dependent on the duration of the isothermal hold. Upon further cooling the strengthening disappears and the stress develops according to the original stress temperature dependence. The observations are discussed in terms of solid solution hardening and precipitation hardening.

Advanced on-chip interconnects using new materials and new integration architectures are necessary for current and future IC chips in order to meet the requirements in performance, reliability and manufacturing cost. Insulating materials with low dielectric constant (low-κ) and conductive materials with low-resistivity have drawn significant attention for their possible applications in IC interconnects. Dual damascene interconnect integration architectures not only offer process simplification and low cost, but also enable the use of low-resistive Cu for interconnect wiring. Use of low-κ materials in dual damascene architecture is challenging due to material and processing issues. In this paper, the evolution of advanced interconnects, materials and technology options, and some recent achievements in advanced interconnect systems of low-κ dielectric and dual damascene architectures for both Al and Cu metallization are reviewed and discussed.

The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

The technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

In order to reduce specific contact resistance at via/interconnect interface and to avoid device degradation with Cu diffusion into dielectrics, via cleaning technology is a critical issue for a scaled down Cu multilevel metallization. Effects of cleaning processes are investigated for CHF3 plasma-etched SiO2/SiN/Cu via-structures. Effects of dilute HF (DHF) cleaning, hydrogen plasma cleaning, oxygen plasma cleaning, hexafluoroacetylacetone (H(hfac)) vapor cleaning, and vacuum anneal cleaning are investigated using an angle-resolved x-ray photoelectron spectroscopy (XPS). Cu contamination removal using dilute oxalic acid (DOA) is investigated using total reflection xray fluorescence analysis (TRXRF). Based on the results, we developed an optimized cleaning sequence which consists of a brief oxygen plasma exposure, DHF dipping, followed by exposure to H(hfac) vapors. The cleaning sequence is effective in obtaining a clean dielectric surface and an oxide-free Cu surface at via bottom. Direct-contacted via structures were fabricated by a dualdamascene process using the cleaning sequence. The specific contact resistance reduces to 20% of the reported values. We expect that the via resistance is low enough to be used in 0.13 µm generation and beyond.

The industry is strongly interested in integrating low–κ dielectrics with Damascene copper. Otherwise, with conventional materials, interconnects cannot continue to scale without limiting circuit performance. Integration of copper wiring with silicon dioxide (oxide) requires barrier encapsulation since copper drifts readily in oxide. An important aspect of integrating copper wiring with low-K dielectrics is the drift behavior of copper ions in these dielectrics, which will directly impact the barrier requirements and hence integration complexity.

This work evaluates and compares the copper drift properties in six low-κ organic polymer dielectrics: parylene-F; benzocyclobutene; fluorinated polyimide; an aromatic hydrocarbon; and two varieties of poly(arylene ether). Copper/oxide/polymer/oxide/silicon capacitors are subjected to bias-temperature stress to accelerate penetration of copper from the gate electrode into the polymer. The oxide-sandwiched dielectric stack is used to overcome interface instabilities occurring when a low-κ dielectric is in direct contact with either the gate metal or silicon substrate. The copper drift rates in the various polymers are estimated by electrical techniques, including capacitance- voltage, current-voltage, and current-time measurements. Results correlate well with timeto- breakdown obtained by stressing the capacitor dielectrics. Our study shows that copper ions drift readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. A qualitative comparison of the chemical structures of the polymers suggests that copper drift in these polymers may possibly be retarded by increased crosslinking and enhanced by polarity in the polymer.

As technology progresses, the need for thinner Cu diffusion barrier caps is becoming more important, and it is advantageous if these barriers have low dielectric constants (κ). Towards this end, we characterized Cu penetration in several thin (35 nm to 70 nm) dielectrics, including silicon nitrides, silicon oxynitrides, an amorphous hydrogenated carbon film, and a methyl silsesquioxane layer. Metal Insulator Silicon (MIS) structures were used as the test vehicle. The barrier dielectrics were deposited on 100 nm thermal oxide which was grown on 2 Ω-cm, n-type Si wafers. After the deposition of 50 nm TEOS capping layers, both Al and Cu dots were evaporated on each wafer through a mask. Both Al and Cu dot samples were stressed at +2.7 MV/cm at 300°C for 10 minutes. For Cu dots, the applied stress pushed Cu ions into the dielectric stack. Stressing Al dots characterized the effects of the stress on the dielectric stacks and the quantity of Na ions in the films. Since C-V shifts are subject to stress-related instabilities in the interfaces as well as within the dielectrics themselves, triangular voltage sweep (TVS) was used after the applied stress to measure the concentration of Cu which reached the underlying thermal oxide film. The sensitivity of the TVS test with the structures used is about 5×109/cm2. Secondary ion mass spectroscopy (SIMS) analyses were performed on some of these samples to verify the electrical results.

The fluorinated low-k dielectrics SiO:F and Teflon AF were investigated for process integration with aluminum and copper interconnects. To minimize fluorine diffusion, several potential barrier materials were deposited onto the fluorinated dielectrics and characterized after heat treatment at temperatures up to 450°C. The barrier layers studied include conventional materials such as Ta, TaN, and TiN, in addition to several novel materials. Barrier layer materials were deposited using evaporation, and sputtering. The materials were characterized using nuclear reaction analysis (NRA) to determine the fluorine concentration profile. A reaction zone was noted at the dielectric-barrier interface on several samples, corresponding to the formation of a fluoride complex. hI some instances, this fluoride layer was self-limiting and prevented further fluorine diffusion through the remainder of the barrier layer.

In order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.

Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the C Is transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.