The release of interstitials from extended defects after ion implantation acts as a driving force behind transient enhanced diffusion (TED). Implantation of Si+ ions into regions of phosphorus-doped silicon provides experimental insight into the interaction of silicon interstitials and dopant atoms during primary damage annealing. The presence of phosphorus influences the morphology of secondary defects during initial nucleation. Transmission electron microscopy (TEM) is used to differentiate between defect types and quantify the interstitials trapped in extended defects. This analysis reveals that phosphorus results in a reduction of interstitials trapped in observable extended defects. The interstitial flux released from the implanted region is also affected by the phosphorus doping. This phenomenon is closely studied using secondary ion mass spectrometry (SIMS) to monitor diffusion enhancements of dopant layers. Shifts in diffused dopant profiles are correlated with the different morphologies of the extended defects and the decay of the silicon interstitial supersaturation. This correlation is used to understand the interaction of excess silicon interstitials with phosphorus atoms.

We studied damage evolution and the influence on defect interactions as a function of Si self implantation dose in p/p+ silicon wafers. Highly boron doped 150 mm diameter silicon substrate wafers with a 2.5 μm thick nominally un-doped epitaxial layer (p/p+) were employed. Due to the misfit strain, misfit dislocations formed during the epitaxial growth process around the wafer edges. This localized dislocation distribution was utilized to study the role of the implant on both the nucleation and growth of the misfit dislocation segments. Triple axis x-ray diffraction was used to determine changes to the strain in the layer due to both the implant and to subsequent annealing. Double axis x-ray topography combined with rapid thermal annealing was used to measure the nucleation and extension of the misfit dislocation segments after annealing. For the lower implantation dose (1012 cm−2) samples, the velocity of dislocations was reduced measurably and the density of newly formed misfit dislocations also decreased significantly relative to regions that received no ion implantation. A higher implantation dose reduced the nucleation and glide velocity further such that neither glide nor nucleation of new segments was detected. SIMS measurements confirmed that the interfacial lattice parameter grading was not appreciably different after an anneal step for the lower implant dose sample, but was measurable for the higher dose sample. In the latter case, transient point defect enhanced diffusion of boron was responsible for the grading. However, the lack of grading in the low dose sample indicates that interfacial grading did not significantly impede dislocation kinetics. This comparison indicates that it is the excess point defects that are produced during implantation that retard both the nucleation and extension of misfit dislocation segments.

The level of sophistication reached by today's Si device fabrication technologies has called for new modeling and simulation schemes, capable of handling the wide variety of interaction mechanisms that govern the complex phenomena that can occur at the atomic level. The kinetic Monte Carlo (KMC) technique seems particularly apt for this task. It takes as input basic materials parameters, derived from ab-initio calculations or from experiments, and is capable of carrying out a detailed simulation up to the dimensions and time scales of current ULSI Si device manufacture. In addition, it can accommodate and efficiently simulate complex interactions between multiple dopant and defect types. We explain the approach and show examples of application in both materials processing and device fabrication. Finally, we present the use of some artificial intelligence techniques (namely, genetic algorithms) that look most promising as methodologies that can easy and efficiently be employed to build the extensive KMC parameter database.

Laser thermal processing (LTP) of Si involves laser melting a preamorphized layer in order to activate dopants and create a low resistivity contact. Defects are often observed to form during the recrystallization of the molten layer. This work focuses on varying the implant conditions and the pre-LTP annealing conditions in an effort to reduce these defect concentrations. The effect of very low temperature anneals (VLTA) and varying dose rates on the amorphous/crystalline interface roughness prior to LTP and the defect density after LTP have been investigated. The amorphous layer was created by a 10 keV 1×1015/cm2 Si+ implant. VLTA were conducted in a nitrogen gas furnace at temperatures between 400°C and 450°C for times between 5 minutes and 60 minutes. These anneals were chosen to minimize recrystallization of the amorphous layer by solid phase epitaxial regrowth. Variation in the dose rate from 0.06 mA/cm2 to 0.48 mA/cm2 was achieved by changing the beam current in the ion implanter. High-resolution crosssectional transmission electron microscopy (HR-XTEM) was used to analyze the effect of the VLTA or dose rate on the amorphous/crystalline interface. Results show that the 400°C 60 minute VLTA or the 0.48 mA/cm2 dose rate reduced the roughness of the amorphous/crystalline interface from over 45Å to around 15Å. This reduction in amorphous/crystalline interface roughness prior to laser thermal processing results in a reduction in LTP recrystallization defects by as much as an order of magnitude.

In this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

We have studied boron profiles by using the ion beam recoil implantation. A boron layer was first deposited onto Si, followed by irradiation with Si ions at various energies to knock the boron. Conventional belief is that the higher the implantation energy, the deeper the recoil profiles. While this is true for low-energy incident ions, we show here that the situation is reversed for incident Si ions of higher energy due to the fact that recoil probability at a given angle is a strong function of the energy of the primary projectile. Our experiments show that 500-keV high-energy recoil implantation produces a shallower B profile than lower-energy implantation such as 10 keV and 50 keV. The secondary-ion-massspectrometry (SIMS) analysis shows that the distribution of recoiled B atoms scattered by the energetic Si ions agrees with our calculation results. Sub-100 nm p+/n junctions have been realized with a 500-keV Si ion beam.

We have investigated the electrical characteristics, junction depth and defect of ultrashallow junctions formed by using a plasma doping procedure. Compared with ultralow energy boron ion implantation at 500eV, the plasma doping process exhibits both a shallow junction depth and a low sheet resistance. The junction depths of the plasma doped samples were 15 nm and 33 nm after annealing for 10s at 900 °C and 950 °C, respectively. For the same junction depth, the sheet resistance of the B2H6 plasma doped sample is an order of magnitude less than that of the 500eV B ion implanted sample. Based on cross-sectional transmission electron microscope (TEM) and deep level transient spectroscopy (DLTS) analysis, the defects formed by the B2H6 plasma doping process can be completely removed by annealing at 950 °C for 10s.

The ion implantation of boron remains the most practical means of forming shallow and ultra-shallow p+/n junctions in silicon. A high conductive junction requires both a large density of dopant atoms and electrical activation amongst these. While it is possible to simply higher doses of boron at lower energies, the potential benefits of the changes are often muted by the electrical deactivation of the boron was occurs through a clustering process. Therefore, it is important to do understanding of the kinetics and transients involved in these proces.

It has been shown that ion implanted boron clusters with interst residual from the implantation process. These clusters are immobile, fractionally or totally electrically inactive, and very thermally state study a series of experiments were conducted in order to investigate processes. In addition to this, a means of utilizing X-ray Diffractio to correlate electrical activity to the rocking curve has been development

We discuss the first use of solid source diffusion (SSD) to form shallow, self-aligned SDEs in a novel device known as the Vertical Replacement-Gate (VRG) MOSFET. This is the only MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. The use of SSD in this novel geometry allows us to transform the precise gate length control afforded by the VRG process into precise, lithography-independent channel length control. In the VRG-nMOS process, silicon nitride offset spacers separate the phosphosilicate glass (PSG) SSD dopant sources from the polysilicon gate. These offset spacers, whose critical dimensions are also controlled by film thicknesses, allow us to precisely tune the gate-source and gate-drain overlaps in order to optimize the capacitance/series resistance tradeoff. These parasitic overlap capacitances have precluded the high-frequency operation of many previous vertical MOSFETs. In this paper, we discuss the SIMS and sheet resistance characterization of shallow phosphorus junctions formed in one-dimensional SSD experiments. We will also discuss the scanning capacitance characterization of two-dimensional doping profiles of VRG-nMOSFETs with gate lengths down to 50 nm.

Amorphous silicon films with B, P, and As implants were activated with thermal anneals that include spiking to the maximum temperature. Films were grown over thermal oxide by chemical vapor deposition as two separately implanted 50-nm layers for manipulating dopant placement and diffusion. Electrical activation was determined by Hall van der Pauw and MOS C-V, and dopant diffusion was profiled by secondary ion mass spectroscopy (SIMS). Flat-band voltage was used to benchmark relative thermal budgets for p-type poly. Temperature-time relationships are used to deduce effective activation energies.

Alleviating transient enhanced diffusion (TED) is one among several issues that has to be solved to realize deep sub-micron CMOS. In this paper we present the influence of hydrogen plasma on TED of boron, along with deep level transient spectroscopic (DLTS) studies on defect evolution as a function of anneal temperature. The studies reveal that TED monotonically increases as a function of anneal temperature up to 650°C, where maximum TED occurs. Further increase in anneal temperature reveals TED reduction. The DLTS reveals a corresponding increase in defect density up to 650°C and then decreases when annealed at 850°C for the same amount of time.

The drive towards developing deep sub-micron CMOS devices places more challenges on semiconductor processing. From the standpoint of doping technology, the challenge is to achieve ultra-shallow p+/n source/drain extension junctions for PMOS. Among the various approaches being pursued to meet this challenge, pre-amorphization was used to curtail channeling of the as-implanted Boron. The effect of pre-amorphization on junction depth and junction sheet resistance in the ultra-low implant energy regime is investigated in this study. Pre-amorphization was achieved with Ge implant. B was implanted at energies of 250eV to 5keV and at a dose of 1×1015cm−2 into crystalline and pre-amorphized wafers. Both spike anneal at 1050°C and furnace anneal at 500°C to 750°C were performed after B implants. In all spike anneal cases, the pre-amorphized wafers exhibit higher sheet resistance and shallower junction depth than crystalline wafers. In all furnace anneal cases, shallower junction depth as well as lower sheet resistance can be achieved with pre-amorphized wafers. Higher pre-amorphization energy induces lower sheet resistance after both furnace and rapid thermal anneal (RTA).

We investigate the residual vacancy defect species after crystallization of amorphous Si (a-Si) by solid phase epitaxy (SPE). To this end, we correlate the total and electronically-active doping concentrations measured by secondary mass spectrometry and spreading resistance analysis, and data from positron annihilation spectroscopy (PAS), which is sensitive to openvolume defects. Float-zone silicon substrates were implanted with boron, phosphorus and both phosphorus and boron ions to create nonuniform doping profiles at degenerate doping levels, after an amorphization step by 29Si+ ions. Samples were vacuum annealed at 600°C to induce SPE, and the SPE rate was measured by time-resolved reflectivity. PAS was used for identification of the impurity-defect complexes. Momentum-resolved PAS measurements enable the detection of phosphorus-vacancy (P-V) and oxygen-vacancy (O-V) complexes.

Factors responsible for the onset of dislocation generation in the fields of localized high stresses have been studied in LOCOS-isolated test structures by means of preferential etching, junction leakage analysis, and computer simulation. A strong correlation between densities of stacking faults and dislocations was observed in the experiments. Defect distributions also correlated to leakage currents. 2D simulations of stresses, interstitial injection, and stacking fault growth during field oxidation showed that maximum resolved shear stress in the structures did not exceed the critical level for dislocation generation and that the agglomeration of silicon interstitial atoms did not play a notable role in dislocation nucleation. Dislocation and stacking fault formation was attributed to surface mechanical damage introduced during plasma processing.

This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (∼100 °C/s) and ∼1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 μm device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 nm.

We analyze the requirements that the International Technology Roadmap for Semiconductors (ITRS) implicitly imposes on the two-dimensional source/drain (SD) dopant profile and translate the results into implant parameters (energy, dose, peak concentration). We do this by determining the voltage drop that the SD current develops across the three main (exclusive of the channel) resistive components in the current path: the spreading resistance in the extension region; the metal-semiconductor contact; and the resistance in the link-up region where the SDregion meets the channel. The largest resistance occurs in the link-up region, followed by the resistance of the contact; the extension contribution is the smallest. The extension resistance requirement can be satisfied by ion-implantation for all generations of the ITRS. The link-up region requires very abrupt lateral profiles, not demonstrated so far by ion-implantation. It is found that such resistance cannot be reduced without impacting the intrinsic device behavior. The contact eventually necessitates dopant concentrations in excess of solid solubility and for NMOS in excess of the fundamental limit of dopant activation.

In summary, we find it is possible to model the extent of diffusion during spike anneals with varying ramp rates by considering the full thermal cycle. These models allow the optimization of RTP ammealing cycles considering the trade-offs between junction depth and sheet resistance. For example, with 1050°C spike anneals, the active dose (and thus sheet conductivity) varies approximately linearly with junction depth. However, faster ramp rates allow the use of higher spike temperatures, with associated higher activation and reduced sheet resistance for the same junction depth.

Work at Bosten University and the University of Washington was supported by the Semiconductor Research Corporation. We would like to thank Eric Perozziello for details and discussion regarding their experimental results.

Clustering equilibrium was studied on silicon on insulator specimens uniformly doped with As at concentrations CAs up to 7.6 × 1020 cm−3. Values of the carrier density n* after equilibration at 700, 800 and 900°C are reported. It is shown that both the concentration and the temperature dependence of n* can be accurately simulated by a simple cluster model detailed in the Appendix. The analysis of the clustering kinetics of these compositions was performed at temperatures in the range 550 to 800°C. It is found that at 800°C the kinetics accurately complies with the rate equation:

-dn/ dt = A{exp[-(E-αn)/kT] - (n0- n)/( n0- n*) exp[-(E-αn*)/kT]

which is the one reported in Ref.[14] complemented by the second term on the right to account for the declustering process. Deviations leading to rates lower than predicted by the above equation are observed by annealing at lower temperatures. The dependence of this phenomenon on composition and temperature is reported.

{311) defects and dislocation loops are formed after ion-implantation and annealing of a silicon wafer. Recent Transmission Electron Microscopy studies by Li and Jones have shown that sub-threshold dislocation loops nucleate from {311} defects. In our study, the conjugate gradient method with the Stillinger Weber potential is used to relax different configurations such as {311} defects with a maximum of five chains and perfect dislocation loops. From the formation energies thus obtained we find that there is an optimal width for each length of the {311} defects. Moreover the relative stability of {311}s and loops is studied as a function of defect size. We observe that at very small sizes the perfect loops are more stable than the {311}s. This may provide an explanation for the experimental observation by Robertson et al that, in an annealing study of end of range damage of amorphized samples, 45% of the loops had nucleated in the first 10 minutes of anneal. Out of these 25% of the loops could not have nucleated by unfaulting of {311}s. We propose that homogeneous nucleation, as against unfaulting of the {311}s, could be the source of these sub-microscopic loops.

In this paper, we discuss the mechanisms by which small clusters evolve through “magic” sizes into {113} defects and then, at sufficiently high dose levels, transform into dislocation loops of two types. This ripening process is mediated by the interchange of free Si(int)s between different extended defects, leading to a decrease of their formation energy. The calculation of the supersaturation of free Si-interstitials in dynamical equilibrium with these defects shows a hierarchy of levels of nonequilibrium diffusion, ranging from supersaturations S of about 106 in the presence of small clusters, through 103 in the presence of {113} defects, to S in the range 100 down to 1 as loops are formed, evolve and finally evaporate. A detailed analysis of defect energetics has been carried out and it is shown that Ostwald ripening is the key concept for understanding and modelling defect interactions during TED of dopants in silicon.