Many semiconductor processing facilities rely heavily on capacitance voltage (CV) analysis for verification of oxidation furnace cleanliness. CV provides an accepted set of electrical test parameters (Vfb, Qm, Tox Dit, etc). that can be used to monitor tube contamination levels during processing. However, two significant drawbacks of the CV technology are a) the need for costly and time-consuming deposition of MOSCAF (Metal Oxide Semiconductor Capacitor) electrodes, and b) the reduction in electrically active contaminants due to the MOSCAP processing sequence. A commercially available noncontacting technology called corona-oxide-semiconductor (COS) analysis is described here which does not require post-oxidation processing, but does measure the fundamental electrical test parameters required for process control and development [2]. The noncontact COS technology is shown to be significantly more responsive to intentionally introduced electrically active contaminants than poly MOSCAP CV. The data indicate that this difference in sensitivity is due to the immediate, processing-free nature of the COS technology.

For future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

We show, for the first time, that E'like centers can be generated in hot hole stressing of short channel metal oxide silicon field effect transistors (MOSFETs). Prior to this study only Pb centers had been directly linked to this stressing phenomenon.

The behavior of small MOS structures (area 3 μm2), subjected to stresses caused by electron injection, demonstrates an obvious non-parallel shift in the tunneling characteristics (NPS effect), measured in the wide current range (3·10-16 -3·10-8 A) from either tunneling interface. This paper describes and compares two different approaches for the NPS effect interpretation: uniform and local degradation models (UDM and LDM). The UDM implies a modification of the oxide tunneling barrier due to area-uniform electron trapping inside the tunneling distance which could lead to the NPS effect [14]. It is shown that any spatial distribution of negative oxide charge is inapplicable to interpret the NPS effect within the framework of the UDM. The second approach uses the assumption of small (area ∼ 10-3 μm2) structure-stable regions (SSR) formed in noncrystalline SiO2 films during thermal growth. Due to the high resistance of SSRs to the degradation - negative charge generation - electron injection is gradually localized in the SSRs, avoiding a screening effect of electron trapping. It is shown that the influence of non-uniformity in the electron injection appears to be more significant, when degraded MOS structure is tested at low voltages (NPS effect).

Hot-carrier effect was studied for different channel doping profiles in nMOSFET devices with effective channel length near 100 nm using a device simulator. The test structures for device simulation were generated using gate oxide thickness of 3 nm. The channel doping profiles used were abrupt- and graded-retrograde types with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations. For accurate device simulation, a hydrodynamic model for semiconductors was used to simulate the non-local transport phenomena in the devices. The simulation results indicate that for ultra-short channel devices, the current drivability and the hot-carrier effects depend on the shape of channel doping profiles. For a given supply voltage, the hot-carrier effects in ultra-short channel devices can be controlled by optimizing the channel doping profiles.

The logarithmic current transients observed after electrical stress of 2 nm thick oxides on silicon show no sign of saturation for times up to 1 Ms. These results contradict the hypothesis that the tunneling distance from oxide defects to an interface is the main source of the dispersive relaxation in our case, and this might very well extend to other cases where such relaxation is observed in MOS devices with thicker oxides.

MOS device stability can be significantly affected by charge trapping in the gate oxide, which changes device parameters and causes serious reliability problems in transistors and memory cells. Hole traps, generated by high-field electron injection, are studied in this work in devices with thermal oxides less than 10 nm thick. PMOS transistors, after various doses of positive and negative Fowler-Nordheim injection and post-stress annealing, are subjected to substrate hot hole injection to investigate hole trapping kinetics. Parameters of hole traps, generated under the stress, are studied as a function of gate oxide thickness and electron injection dose.

The relation between electromigration and microstructure for three types of Al lines with different microstructures has been studied. The lines were made by recrystallization of Al in a SiO2 groove pattern. They were either truly bamboo with grains of on average 3 μm long or distorted (i.e. with dislocations) single-crystals. In addition, conventional, polycrystalline Al lines with grains of on average 230 nm were made. The lines were lifetime-tested (200 °C,j=2, 5 and 8 MA/cm2) and subjected to l/f noise measurements (from 200 to 500 K).

The bamboo and single-crystalline Al lines showed the same, although weak, 1/ƒ noise. This observation demonstrates that other mechanisms than thermal motion of atoms at grain boundaries can cause noise. It is suggested that dislocations are the sources for noise in our samples. The measured activation energy (0.8 eV) is in agreement with the activation energy for pipe diffusion along dislocation lines.

The lifetime-tests showed significantly higher times to failure for the single-crystalline and bamboo lines as compared to polycrystalline lines. Preliminary results indicate slightly higher lifetimes for the bamboo than for the single-crystalline lines. It is concluded that interface diffusion is the main mechanism for electromigration in truly bamboo or single-crystalline lines. Our measurements demonstrated that dislocations are important in the formation of l/ƒ noise and interfaces in the formation of electromigration damage.

Novel metal deposition stack and damascene processing methods have been used to fabricate electrically isolated parallel arrays of 1.0 μm deep aluminum-alloy interconnect trenches varying in width from 0.5 μm to 16 μm. The grain size and crystallographic texture of the Al in these trenches has been characterized using transmission electron microscopy (TEM) and local electron backscattered diffraction (EBSD), respectively. Narrow lines (0.5 and 1.0 μm wide) have a bamboo microstructure, intermediate widths (2.0 μm wide) are nearly bamboo, and wide lines (4.0 μ and wider) are polycrystalline. The <111> texture of the lines degrades with decreasing linewidth. A secondary <100> component is demonstrated and its origin proposed. The electromigration reliability of the narrow damascene Al lines was measured, and the observed enhancement of damascene Al interconnects compared to conventionally-fabricated Al interconnects is correlated with the microstructure.

The electromigration lifetime of aluminum interconnect lines shows a strong dependence on the quality of the texture in the metal. This observation has been explained in terms of a decreased diffusivity along the grain boundaries, generally the dominant path for diffusion and void growth. As the texture in the metal is strengthened, atomic order along the grain boundaries is increased, and diffusion is suppressed.

In this paper, we examine passivated Al-0.5wt%Cu interconnect lines having either Ta Al underlayers or conventional Ti/TiN underlayers. Rocking curve measurements confirm that Al deposited on TaAl has a very strong (111) texture (FWHM ∼ 0.6°) compared to Al on Ti/TiN (FWHM ∼ 6°). Interconnect lines of both types were electrically stressed at 225°C and 250°C for 20 hours at a current density of 3 MA/cm2. The lines were then stripped of passivation, and the void numbers, sizes, and morphologies were determined.

Analysis of the void data gave a surprising result: the void volume in the highly-textured Al was greater than in the conventional Al. However, voids in the conventional Al were observed to follow grain boundaries across the width and sever the line, while such destructive void growth was not observed in the highly-textured Al. Instead, voids grew either with a faceted shape or along the line edge, never extending across the line width. Modeling electromigration in the surrounding microstructures shows that void locations in the highly-textured lines are often independent of the surrounding grain boundaries. In this case, the line sidewalls appear to be significant mass transport paths. Since these paths do not cross the line width, voids growth across the line is difficult. This resistance to fatal damage makes highly textured aluminum a promising interconnect material.

Formation and morphological change of voids induced by electromigration in polycrystalline Cu interconnects on TiN have been investigated at various current density conditions at elevated temperatures. At first voids were formed at grain boundaries, then they grew further to elongate in the electric field direction. Void elongation parameter (a ratio of void diameters in longitudinal to lateral directions to the electric field) was 2.53 when the current density was 9×106A/cm2, while it was 1.31 when the current density was 3×106A/cm2at 400°C, 50h. Occurrence of void elongation is enhanced with increase in current density, and its relationship to grain boundaries are discussed by FIB-SIM image analysis.

Cu film characteristics and in-situ observation of electromigration voiding in passivated Cu lines are reported. Measured grain size distribution show a median grain size of 0.4 μm. A 3 μm wide, 800 μm long line passivated with 5000 Å of SiO2 was tested in a high voltage scanning electron microscopy (HVSEM), enabling dynamic in-situ events to be recorded. Electromigration voiding in this line showed some similarity to that previously observed in polygranular Al lines. Transmission electron microscopy was used to study the microstructure of the passivated Cu lines.

PVD-TixSiyNz films formed by reactive RF-magnetron co-sputtering of Ti and Si in Ar/N2 are evaluated as a diffusion barrier between Cu and Si. A complete range of compositions are obtained by Ti targets inlaid with Si. Film composition is controlled by the target ratio of titanium to silicon and N2 partial pressure. Electrical results versus thermal history for films of∼6–18% Si as well as the composition and microstructure as determined by Rutherford back scattering (RBS), TEM and electron diffraction are reported. These films are an amorphous matrix with imbedded nanocrystals of titanium nitride as-deposited and undergo phase separation to yield titanium nitride and silicon nitride after a 1000°C anneal. As-deposited compositions which lie above the TiN-Si3N4 phase line yield crystals of TiN. Compositions below the TiN-Si3N4 phase line yield crystals of Ti2N. Bulk resistivity as-deposited (<400μω-cm) is acceptable for use as a contact liner/barrier material and improves with annealing. Si pn-diodes metallized with 20nm Ti40Si15N45 and Cu show no significant increase in reverse leakage current at anneal temperatures below 700°C.

Amorphous Ta-Si-N thin film was deposited by dc sputterring of Ta5Si3 target in (Ar+N2) atmosphere. The crystal structure and the thermal stability of Ta-Si-N thin films were investigated by XRD, RBS, AES, Nomarski microscope, and TEM. When the concentration of nitrogen in Ta-Si-N thin film was higher than 40 at.%, the Ta-Si-N thin film remained the amorphous state after the annealing at 1100°C for 60 min. In this case, the Cu diffusion was prevented by the amorphous Ta-Si-N thin film even if the annealing temperature increased up to 900°C for 30 min. Whereas, the Ta-Si-N thin film with nitrogen concentration less than 40 at. % was transformed from the amorphous to the polycrystalline TaSi2 phases after the annealing at 900°C for 60 min and failed to prevent the Cu diffusion after the annealing at 700°C for 30 min.

Electromigration induced resistance changes in short Al lines have been studied by high-resolution AC bridge measurements. The samples were pure, unpassivated Al lines having a length of 3, 5, 8, 12, 17 or 100 μm, a width of 2 μm, and a film thickness of ∼100 nm. Depending on current density and sample length the induced resistance changes fully recover or do not recover after removal of the DC stressing current. The transition from recoverable to non-recoverable behavior is clear-cut and is characterized by a constant critical current density - sample length product. The value of this product is close to the value of the constant critical current density - sample length product characterizing the occurrence of drift in a drift velocity experiment. Inspection of the lines after current stressing by atomic force microscopy revealed that non-recoverable resistance changes are caused by the growth of a single void, hillock or hillock/void pair. Negative resistance changes correspond to the growth of a hillock and positive resistance changes to the growth of a void. The magnitude of the non-recoverable resistance changes can be very well estimated from the dimensions of the void or hillock. The rate of change of the non-recoverable resistance changes (or the growth rate of a void or hillock) scales linearly with the current density.

The characteristic time of the relaxation process of the recoverable resistance scales with the sample length squared. The temperature dependence of the relaxation time shows a good Arrhenius behaviour with an activation energy typical for grain boundary diffusion in Al. The maximum magnitude of the recoverable resistance changes is ΔR/R∼5×10∼-4. The time and temperature dependence of the recoverable resistance changes can be very well explained by the mechanical stress evolution model of Korhonen et al. The evolution of the stress is reflected in changes of the electrical resistance by the piezoresistance effect. A good agreement is found between maximum observed recoverable resistance change and the maximum stress in the line. The good understanding of the resistance changes induced by electromigration in short lines makes this geometry very attractive for studies of fundamental aspects of electromigration in thin film conductors.

The time-dependence of the growth of Al2Cu precipitates in Al-Cu(lat% Cu) thin films is studied by means of resistance measurements at different temperatures. The samples are annealed at 400°C for 1 hour, and then quickly cooled down to room temperature. Afterwards, the samples are heated within one minute to a measurement temperature between 140 °C and 240 °C. Growth of precipitates causes a well defined decrease in resistance. The observed resistance decrease does not follow an exponential decay. In the investigated temperature range the resistance decrease can be accurately modelled by (R(t)-R∞) = (Ro-R∞)exp(-(t /τ)n), with the time constant τ= τ0 exp(Ea / kT). Excellent fits were obtained resulting in n = 0.66±0.05, independent of temperature, and Ea= 0.81±0.03 eV. This value for the activation energy agrees very well with the activation energy that has been reported in literature for both electromigration failure in Al-Cu and grain-boundary diffusion of Cu in Al. The value we found for n is intriguingly close to 2/3 and deviates strongly from the values of n reported for bulk Al-Cu (n = 1.5–1.8) in the same temperature range.

X-ray microdiffraction was applied to study the thermal and electromigration strains in 10 μm-wide Al conductor lines with 10 μm spatial resolution. X-rays were collimated either by pinholes or by tapered glass capillaries to form x-ray microbeams. Measurements were made in a symmetric-reflection geometry so that the strains normal to the sample surface could be examined at different positions along the conductor lines. Results of thermal strain measurements show that the SiO2 passivation plays an important role in limiting relaxation of in-plane compressive thermal stresses in the Al lines, but that the passivation is not effective in confining the overall thermal expansion of the Al line along the film normal. Electromigration strain measurements show that a linear stress gradient developed within the first hour of electromigration. The magnitude of the stress gradient changed little until fast stress relaxations occurred near the anode end of the line. Possible mechanisms are discussed in light of these observations.

The thermal conductivity of interlevel dielectrics (ILD) in interconnect structures is an important parameter in determining the temperature rise in the interconnects during use. Numerous researchers have previously shown that the thermal conductivity of thin film dielectrics can be significantly lower than that of bulk materials. As new materials, such as low-dielectric constant materials, are considered for use as ILD's, methods are needed for measuring the thermal conductivity of the these materials to determine whether they can adequately conduct heat away from interconnect lines. Many methods reported in the literature use patterned metal lines atop the dielectric on a Si substrate as combination Joule heaters and temperature sensors, and extract the thermal conductivity from a model of heat conduction through the dielectric to the substrate. One drawback of these methods is the lack of agreement of the conductivity determined from the different techniques. For example, a thermal conductivity ranging from 0.6 to 1.4 W/m-K was calculated for a 1.25 μm thick PTEOS oxide using five different methods on the same test structure. In this paper we present a unique combination of test structures, experimental methods, and heat conduction models that highlight the limitations of some of the models and methods. We also show good agreement in the thermal conductivity determined from both an experimental method and a finite element model, and suggest that these two techniques yield an accurate measure of the thermal conductivity of thin film dielectrics.

Thin film delamination and sub-surface cracking represent important reliability issues for the semiconductor and thin film magnetic hard disk industries. Detecting such defects is often difficult and requires complicated specimen cross-sectioning and imaging. Because the sample preparation process itself may cause crack growth, such a method may be used only as a qualitative tool for defect characterization. In the present work, we introduce an in-situ non-destructive technique for detecting sub-surface cracks by continuously monitoring the contact stiffness while dragging a probe across a smooth surface at an ultra light load. As the probe encounters a sub-surface crack, the local contact stiffness decreases dramatically. The amount of reduction in contact stiffness depends on the crack size and geometry and the position of the crack relative to the surface. Results of the scanning stiffness microscopy experiments conducted on hard carbon and chromium thin films are described and discussed.

Opportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.

Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.