Recent events in the high-performance computing industry have concerned scientists and the general public regarding a crisis or a lack of leadership in the field. That concern is understandable considering the industry's history from 1993 to 1996. Cray Research, the historic leader in supercomputing technology, was unable to survive financially as an independent company and was acquired by Silicon Graphics. Two ambitious new companies that introduced new technologies in the late 1980s and early 1990s—Thinking Machines and Kendall Square Research—were commercial failures and went out of business. And Intel, which introduced its Paragon supercomputer in 1994, discontinued production only two years later.

During the same time frame, scientists who had finished the laborious task of writing scientific codes to run on vector parallel supercomputers learned that those codes would have to be rewritten if they were to run on the next-generation, highly parallel architecture. Scientists who are not yet involved in high-performance computing are understandably hesitant about committing their time and energy to such an apparently unstable enterprise.

However, beneath the commercial chaos of the last several years, a technological revolution has been occurring. The good news is that the revolution is over, leading to five to ten years of predictable stability, steady improvements in system performance, and increased productivity for scientific applications. It is time for scientists who were sitting on the fence to jump in and reap the benefits of the new technology.

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.

To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

For devices with feature sizes below 0.18 μm, it is desirable to have materials with a dielectric constant below 2.5 as interlayer dielectrics. Polymeric materials are possible candidates. There are two main strategies to grow polymeric films. The most widely used method is the spin-on technique. The other method is by vapor deposition. Although vapor deposition is less common, it has several attractive features that look quite promising, especially when the wafer size becomes very large.

There are several advantages to vapor-deposited polymers:

(1) The deposition of the polymers is a dry process. It is solvent-free and does not produce waste. No remedial measures are necessary to take care of the waste. The process is attractive from both energy-conservation and environmental considerations.

(2) They can provide an extremely uniform coating over a very large area. For 200-mm wafers, for example, one can achieve better than 2% uniformity for vapor-deposited parylene (a type of polymer to be described later) films. Similar uniformity can be expected for future 300-mm wafers.

(3) Many vapor-deposited polymers possess superior gap-filling capability. Small vias and trenches of very high aspect ratios can be filled without voids.

There are some shortcomings in vapor deposition of polymeric thin films. First of all, except for some special cases, processing issues for these materials are not well-studied. Manufacturing equipment is not well-developed.

Low-dielectric-constant materials (k < 3.0) have the advantage of facilitating manufacture of higher performance integrated-circuit (IC) devices with minimal increases in chip size. The reduced capacitance given by these materials permits shrinkage of spacing between metal lines to below 0.25 μm and the ability to decrease the number of levels of metal in a device. The technologies being considered for low-k applications are chemical vapor deposition (CVD) or spin-on of polymeric materials. For both types of processes, there are methods and materials capable of giving k < 3.0 dielectric stacks. This article will focus on the spin-on approach and discuss the properties of both organic and inorganic spin-on polymers.

While CVD SiO2 has been the mainstay of the industry, spin-on materials are appropriate for many dielectric applications. Polyimides have applications as electrical insulators, and traditional spin-on silicates or siloxanes (k > 3.0) have served as planarizing dielectrics during the last 15 years. The newer spin-on polymers have greatly enhanced mechanical, thermal, and chemical properties, exhibiting lower dielectric constants than the traditional materials.

As feature sizes in integrated circuits approach 0.18 μm, problems with interconnect resistance-capacitance (RC) delay, power consumption, and crosstalk become more urgent. Integration of low-dielectric-constant (k) materials will partially mitigate these problems, but each candidate with k significantly lower than that of dense silica (k ∼ 4) suffers disadvantages. Current low-k commercialization emphasizes spin-on glasses (SOGs) and fluorinated SiO2 with k > 3, and a number of polymers are under development with k in the range of 2–3. These suffer from potential problems including thermal stability, mechanical properties, low thermal conductivity, and reliability. For some low-k materials, a protective liner covering the conductor is necessary. Although the material k is often cited, the value of practical concern is the effective k, which may be quite different because of this protective liner. As feature sizes shrink, the presence of the liner becomes more problematic and necessitates even lower k materials.

Another approach employs nanoporous silica with k of ∼1–4. Porous silica has been classified as an aerogel (dried supercritically) or as a xerogel (dried by solvent evaporation). We use the term nanoporous silica since it captures the key material properties that may be independent of how the films are processed. The ultralow dielectric constant results from porosity incorporation. For a porous material, the dielectric constant is a combination of that of air (∼1) and of the solid phase. The variation of k with porosity (volume fraction of pores) appears in Figure 1.

As on-chip device densities increase and active device dimensions shrink, signal delays and noise increase due to capacitive coupling and crosstalk between the metal interconnections. Since delays, noise, and power consumption all depend critically on the dielectric constant of the separating insulator, much attention has focused recently on replacing standard silicon dioxide with new intermetal dielectrics (IMDs) having dielectric constants considerably lower than conventional oxide (k = 3.9–4.2). On-chip silicon dioxide insulators are currently deposited by gas-phase techniques such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. Silicate films may also be formed at lower temperatures by sol-gel procedures. In the sol-gel process, typically an orthosilicate ester is hydrolyzed with water. This often occurs in an organic solvent to form a soluble, partially condensed polymer (sol) that can be spun on a substrate to produce a solvent-containing film. Subsequent solvent removal and curing results in the silicate film. The process involves hydrolysis to generate polyfunctional silanols followed by condensation polymerization to eventually yield a gel. Since both processes involve the substantial loss of volatile materials, considerable shrinkage occurs (75–85% is typical). Inhomogeneity of shrinkage or shrinkage on constraining substrates can often lead to cracking unless the films are very thin (often <1 μm). In the sol-gel process, a variety of techniques are employed to avoid capillary-driven cracking forces, including (1) very slow drying, (2) drying with supercritical fluids, or (3) chemically controlled condensation.

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.

To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

Low-k organic polymers such as polytetrafluoroethylene (PTFE) are promising materials for use as interlayer dielectrics (ILD) because their dielectric constants are generally lower than those of inorganic materials. However poor adhesion with Si substrates, poor thermal stability, and production difficulties have hindered their use in microelectronics.

On the other hand, plasma-enhanced chemical vapor deposition (PECVD) of polymer films (plasma polymerization) has many advantages that help to overcome these problems. Plasma-enhanced chemical vapor deposition uses a glow discharge to create activated species such as radicals and ions from the original monomer, and the polymer films are deposited through various gas-phase and surface reactions of these active species, including ablation of the deposited film. No water is generated during plasma polymerization, and the influence of a solvent can be ignored. Also a layered structure that promotes adhesion can be easily fabricated by changing the source compounds.

Recently the use of fluorinated amorphous carbon thin films (a-C:F) as new low-dielectric-constant interlayer dielectrics has been proposed. These thin films have an amorphous C–C cross-linked structure (including sp3 and sp2 bonded carbon) and have the same C–F bonds found in PTFE. The strong C–F bonds decrease the dielectric constant, and the C–C crosslinked structure maintains the film's thermal stability. The a-C:F film can be deposited from fluorocarbon source materials using PECVD. Typically fluorocarbons such as CF4, C2F6, C4F8, and their hydrogen mixtures are used as source materials. First the a-C:F films for low-k ILD, with a dielectric constant of 2.1, were deposited from CH4 + CF4 mixtures by using parallel-plate PECVD.

As the dimensions of ultralarge-scale-integration devices scale to smaller feature sizes and larger die dimensions, the resistance-capacitance (RC) delay of the metal interconnect will increasingly limit the performance of high-speed logic chips. This is because the transistor capacitance and resistance both scale to lower values as the feature size is reduced, while both the line-to-line capacitance and resistance of the metal-interconnect lines increase as their dimensions decrease. For interconnects 5-mm long, the crossover feature size at which the interconnect delay dominates the transistor delay is approximately 0.5 μm. Since this interconnect RC delay increases roughly quadratically with decreasing feature size versus the historical quadratic reduction in transistor delay, device designers currently face difficult barriers to continued performance increases with scaling. Figure 1 presents the components of the RC delay for a single-transistor/single-interconnect combination with 0.35-μm feature sizes. The total delay can be broken into four additive components: the transistor delay R0C0, the interconnect delay rLcL, and the two transistor/interconnect cross terms where R0 and C0 are the transistor resistance and capacitance, r and c are the specific resistance and capacitance, and L is the interconnect length. As can be seen for interconnect lengths less than about 100-μm long, the intrinsic transistor delay dominates. However for interconnect lengths between approximately 100 μm and 10 mm, the resistance of the transistor coupled with the capacitance of the interconnect dominates the combined delay, resulting in a linear increase in delay with increasing line length.