The diffusion barrier properties for ultrathin Ru/Ta and Ru/TaN bilayer structure as the copper diffusion barrier are compared. Cu, Ru, Ta and TaN thin films are deposited by using the ion beam sputtering technique. The experimental results show that the thermal stability of the Cu/Ru/Ta or TaN /Si structure is much more improved than that of the Cu/Ru/Si structure without the interlayer. However, the Cu/Ru/TaN/Si shows better thermal stability than the Cu/Ru/Ta/Si structure, which should be attributed to the amorphous nature of the TaN interlayer. The microstructure evolution of the Cu/Ru/Ta (TaN)/Si structure during annealing is discussed. The results show that the Ru/TaN bilayer can be a very promising diffusion barrier in the future seedless Cu interconnect technology.

A novel tantalum precursor, bis(ethylcyclopentadienyl)hydridocarbonyltantalum (Ta(EtCp)2(CO)H EtCp:ethylcyclopentadienyl), for chemical vapor deposition (CVD) and atomic layer deposition (ALD) was synthesized. The molecular structure of this precursor was determined by 1H and 13C NMR, IR, ICP-AES and elemental analysis. This precursor is liquid at room temperature, and its vapor pressure and decomposition temperature indicates that this precursor is suitable for CVD and ALD process.

The composition analysis of metal tantalum films deposited by thermal CVD revealed that the concentration of carbon was larger than tantalum. On the other hand, an argon plasma CVD technique reduced the carbon concentration drastically.

We have observed abrupt, reversible resistance changes during electromigration (EM) testing of 0.16μm thick, 100μm long damascene Cu conductor lines with TaN liners and W vias. Lines of 0.2μm, 0.8μm and 2μm widths were tested and compared. The tests were conducted at temperatures of 300C – 350C and with current densities of 0.6 × 106 A/cm2 to 1.6 × 106A/cm2. In most cases an incubation period with negligible resistance increase is followed by a period of continuous, gradual resistance increase, attributed to formation and growth of voids in the conductor line. With further EM, the resistance curves show spike like features, with a sudden resistance increase, followed by a resistance decrease, often to values close to those before the start of EM. In other cases, no resistance decrease occurs, and the line fails. We present resistance data, microstructural observations and thermal calculations that suggest that the resistance decrease results from sudden, local Joule heating melting of conductor line segments and voids being partially filled by the back-flowing liquid Cu, which then solidifies. In some cases line failure results from liquid Cu erupting through the top surface passivation layer, rather than flowing back to fill voids in the line.

Porous organosilicate materials produced by plasma enhanced chemical vapor deposition are the leading candidates for back-end-of-line dielectric insulators for IC manufacturing at 45nm design features and beyond. The properties of porous organosilicate glass films of dielectric constant k=2.50 ± 0.05 formed using diethoxymethylsilane and five different porogen precursors with an ultraviolet post treatment are reported. By varying the porogen precursor type pore sizes of 1-2 nm (equivalent spherical diameter) and porosities in the range of 24-31% were measured. While there were no observable trends in pore size with the molecular volume or plasma reactivity of the porogen precursor, modulus values ranged from 6.6 to 10.8 GPa. Porous films with the highest mechanical properties were found to have the highest matrix dielectric constant, highest network connectivity (lowest methyl content), and highest density. Within this process space, maximizing the network connectivity of the film was found to be more important to mechanical properties than lowering the total porosity. In effect, the choice of porogen precursor dictates the film morphology through its impact on the organosilicate glass matrix and pore size.

We have carried out measurements of electromigration-induced strains in copper conductor lines using microbeam energy dispersive x-ray diffraction. Strains developed in random texture damascene Cu 2μm-wide, 0.16 μm-thick conductor lines with TaN liners in low-k dielectric during electromigration at 350°C are much smaller than electromigration-induced strains in (111) fiber texture Al-on-Si, 10μm-wide, SiO2 passivated conductor lines. The reasons for these differences in electromigration behavior may involve the different roles of grain boundary and interface diffusion paths and the different passivation structures and materials for the two types of samples.

Understanding thermal conduction in interlayer dielectrics (ILDs) is important for the optimal design of interconnect layers in backend semiconductor processing for future high-performance nano-scale devices. Reduced thermal conductivity of porous ILDs for example can adversely affect the temperature rise in the embedded metal lines leading to un-desirable reliability issues and design constraints. In this paper, we report results of our theoretical and experimental investigation of thermal transport in amorphous and porous dielectrics. A phonon-hopping model has been adapted to calculate the thermal conductivity in disordered materials. The value of hopping integral has been calculated by comparing the modeling results with experimental data for various amorphous and porous materials. The model shows reasonable agreement with experimental data for various amorphous materials including SiO2 and other glasses over a wide temperature range from 50K – 300K. The model suggests that the hopping of localized high frequency phonons is a dominant thermal transport mechanism in such material systems.

Chemical formulations for the electrochemical mechanical planarization (ECMP) of copper must contain constituents that are stable at anodic potentials. A key component of the formulation is a corrosion inhibitor, which is required to protect low lying areas while higher areas are selectively removed. Organic compounds, which adsorb on copper at low overpotentials and form a film by oxidation at higher overpotentials, may be particularly useful for ECMP. The objective of this work is to evaluate the effect of two inhibitors on copper dissolution in oxalic acid based systems using an electrochemical quartz crystal microbalance (EQCM) technique. By recording current as well as mass changes during the application of potential to electrodeposited copper films, the extent and mechanism of inhibition of sulfhydryl based acid (SBA) inhibitor has been explored.

In a crystallographic study of stress induced voiding of copper interconnect, the planar electron backscattered diffraction analysis showed that the void was initiated at the triple junction of the grain boundaries, not at the junction of the twin boundary and grain boundary. By using stepwise cross-sectional crystalline investigation for the void, it was possible to rebuild 3D crystalline structure near the void. From the stress calculation based on the measured crystalline structures, the hydrostatic stress was highly concentrated at the triple junction of the twin boundary and grain boundary, but experimentally, there was no voiding at that. The voiding in the copper interconnect may depend mainly on the boundary instability.

The measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

The implementation of porous low-k and ultra-low k dielectrics to reduce RC delay in integrated circuit interconnect wiring has been fraught with numerous challenges. The obvious challenges of materials design and preservation of the desired electrical and mechanical properties upon subsequent processing have been significant. The vulnerability of these films to damage from fast ion and radiation damage will be discussed in the context of post-deposition processing (including low-k cure and plasma processing damage). This paper attempts to review the challenges associated with destructive and non-destructive measurement of low k dielectric films with respect to underlying physical principles of the metrology. Metrology techniques, assumed to be non-destructive based on experience with dense silicon dioxide, will be discussed with regards to newer and more fragile low-k dielectric films.

Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The main factors requiring attention and careful control are the activation energy related to the dominating diffusion mechanism, the resulting median lifetimes, and the lognormal standard deviation of experimentally acquired failure time distributions. Whereas the origin of the EM activation energy and the behavior of median lifetimes with continuing device scaling are relatively well understood, detailed models explaining the origin and scaling behavior of the lognormal standard deviation are scarce. The statistical behavior of EM-induced void sizes and resulting lifetime distributions appear to be explainable by geometrical variations of the void shapes and the consideration of kinetic aspects of the EM process. Using these models, expected lifetime distributions for future technology nodes can be simulated from current, experimentally obtained void size and lifetime distributions. These simulations have to include geometrical factors of the EM test structures and actual, on-chip interconnects, as well as kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. By extrapolating the expected lifetime distributions for future technology nodes from current EM data, it is possible to predict when insertion of new process schemes, such as Cu-alloys and/or metallic coating of the Cu/passivation interface is required.

This article shows the root cause of Cu corrosion and sulfur contamination due sulfite vapor reflow through drainpipe of load cup to the original three-step Cu CMP equipment. Now, we provide a solution which to modify the arrangement of the drainpipe in original three-step Cu CMP equipment. This is an effective implement for reduction the defects of Cu corrosion and sulfur contamination from long-term observations.

Deposition steps in CVD and ALD applications usually not only cover the surface of the substrate surface but also the walls of the chamber inside. Regular removal of those residuals has to be done to obtain stable and repeatable deposition results with uniform surfaces at acceptable particle levels. The high requirements to sustain stable processes has lead to more frequent chamber cleans. NF3 has emerged as the main clean gas for remote clean applications. While it meets the above mentioned requirements and is considered to fit easily into the fab gas supply it is relatively expensive. The work presented here investigates argon/nitrogen diluted fluorine (F2) as an alternative clean gas with a significantly reduced environmentally destructive global warming emission (GWP). The cleaning behaviour with respect to different materials (SiON, TaN, TiN, W, SiO2) was studied. It is found that in general argon/nitrogen diluted fluorine achieves etch rates comparable to those obtained by NF3 when the comparison is based on the amount of fluorine transported into the reactor.

Thermally-grown 220nm-thick silicon oxide layers were implanted at room temperature with 300keV Xe at doses ranging from 0.5 to 5x1016Xe/cm2. As-implanted samples exhibit bubbles in silicon oxide for all doses. Annealing at T≤400°C results in the disappearance of bubbles from SiO2 layer for the dose of 1x1016Xe/cm2. But for the higher doses of 3.5 and 5x1016Xe/cm2, the bubbles are very stable and remain in the sample even after very high thermal annealing. Capacitance measurements show a strong decrease in the dielectric constant k of the implanted SiO2 sample from 4 (reference sample) to 1.5.

Bonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.

Real contact area between a CMP pad and wafer is a key factor in local contact pressure, friction and pad wear, all of which impact material removal and defect formation. A new optical method is introduced that quantifies the real contact area during polishing. Confocal reflectance interference contrast microscopy (C-RICM) uses a single focal plane to image the pad-wafer contact interface. A sapphire cover slip is used to provide optical transparency and to match the refractive index of the pad. Imaging the pad surface through the cover slip reveals areas of no reflection (pad-cover slip contact), areas of reflection (non-contact), and interference fringes (near contact). The C-RICM method was validated using micro-fabricated pads having uniform arrays of cylindrical surface structures of known contact area. Experiments conducted on porous polyurethane pads revealed that the real contact area is less than 10% of the total presented area. However Greenwood-Williamson (G-W) theory, widely used in CMP material removal models, predicts a contact area at least a factor of ten smaller. The discrepancy was found to result at least in part because the individual contact zones are not elliptical as assumed in G-W theory. In fact many contacting structures are crescents located at the perimeter of individual pores. These findings underscore the need for accurate control of pore density and morphology in polishing pads, in both initial manufacture and surface conditioning during CMP. The C-RICM method allows non-destructive benchmarking of polishing media in terms of pad-wafer contact, essential for developing improved pad architectures that achieve lower CMP defect levels.

The technique of channel cracking is used to study the crack growth in SiOCH low-k films. Various film thicknesses are produced using consecutive PECVD deposits on silicon substrates in up to the critical thickness for which spontaneous cracks appear. After determining mechanical properties and residual stresses of these films, samples are cleaved, and subjected to four-point bending tests. During the loading in ambient environment, cracks propagate from defects due to cleavage. Propagation of these cracks is observed in situ in order to correlate crack growth velocities to film thickness and total stress in the film. These results allow plotting crack growth rate versus stress intensity factor for crack velocity varying from 10-9 to 10-4 m/s for a stress intensity factor about 0.1 MPa√m. Moreover, in this range of velocities a model is proposed for this material to determine the film stress required to produce channel cracking, for a given film thickness.

A low temperature plasma etching process for patterning copper interconnects is proposed as a solution to the size effect issue in the resistivity of copper. Key features of this etching process based on a previous thermochemical analysis of the Cu-Cl-H system are discussed. Potential benefits of a subtractive etching scheme based on this process in comparison with the damascene scheme for copper-based interconnect processing in sub-100 nm features are presented in the context of the ITRS roadmap. Preliminary experimental work on plasma etching of Cu thin films using the proposed process is discussed.

The use of low dielectric constant materials in the on-chip interconnect process reduces interconnect delay, power dissipation and crosstalk noise. To achieve the requirements of the ITRS for 2007-2009 minimal sidewall damage from etch, ash or cleans is required. In chemical vapor deposited (CVD) organo-silicate glass (OSG) which are used as intermetal dielectric (IMD) materials the substitution of oxygen in SiO2 by methyl groups (-CH3) reduces the permit-tivity significantly (from 4.0 in SiO2 to 2.6-3.3 in the OSG), since the electronic polarizability is lower for Si-C bonds than for Si-O bonds.

However, plasma processing for resist stripping, trench etching and post-etch cleaning removes C and H containing molecular groups from the near-surface layer of OSG. Therefore, compositional analysis and chemical bonding characterization of structured IMD films with nanometer resolution is necessary for process optimization.

OSG thin films as-deposited and after plasma treatment are studied using X-ray absorp-tion spectroscopy (XAS) and electron energy loss spectroscopy (EELS). In both techniques, the fine structure near the C1s absorption or energy loss edge, respectively, allows to identify C-H, C-C, and C-O bonds. This gives the opportunity to differentiate between individual low-k mate-rials and their modifications. The O1s signal is less selective to individual bonds. XAS spectra have been recorded for non-patterned films and EELS spectra for patterned structures. The chemical bonding is compared for as-deposited and plasma-treated low-k materials. The Fluo-rescence Yield (FY) and the Total Electron Yield (TEY) recorded while XAS measurement are compared. Examination of the C 1s near-edge structures reveal a modified bonding of the re-maining C atoms in the plasma-treated sample regions.

Fabrication of air gap features have been achieved by three processes utilizing the diffusion of materials through a porous OSG layer. The first process involves the decomposition of a PECVD deposited organic material, either thermally or via UV anneal, to create a void with the decomposition by-products diffusing through the porous OSG layer. The second process uses the etch selectivity of XeF2 or BrF3 towards silicon versus OSG to diffuse through the porous OSG layer to etch the underlying silicon. Finally the water solubility of films such as GeO2 or B2O3, which can be easily deposited by PECVD, can be utilized for void formation via dissolution of the sacrificial inorganic layer through the porous OSG.