We have studied the growth of GaAs, InxGa1−xAs, and AlxGa1−xAs on on-axis GaAs (111)B substrates by MBE. RHEED patterns are used to identify different growth conditions. Using the optimized growth parameters, GaAs and Al0.3Ga0.7As films with surface defect densities (observed under an optical microscope) of less than 50 cm−2 were routinely achieved. No significant differences in surface morphology and carrier concentration were found between As4 and As2 if their mass fluxes are the same. A Hall mobility of 30,000 cm2V−1s−1 at 77 K was obtained for a GaAs film with a free electron concentration of 2×1015cm−3.

Etching with an electron cyclotron resonance (ECR) source provides several advantages over conventional reactive ion etching (RIE). In this work, the results of GaAs and InP etching using a multipolar ECR source are presented and compared to RIE. The effects of microwave and rf power, gas composition, pressure, and source to sample distance on the etch characteristics of GaAs and InP were evaluated. Three different etch gases were used including CCl2F2, BCl3, and Cl2. The influence of microwave power on etch characteristics is compared to conventional parallel plate system using rf power alone.

A dry etch fabrication technology for high-speed AlInAs/InGaAs Heterojunction Bipolar Transistors (HBT's) utilizing low-damage Electron Cyclotron Resonance (ECR) CH4/H2/Ar plasma etching is detailed. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). Devices with 2 × 4 μm2 emitters demonstrated current gains of 30–50 with ft and fmax values of ≥ 80 GHz and ≥100 GHz respectively. The structure employs a two-stage collector to achieve breakdown voltage (Vceo ) of 7V. The combination of processing and layer structure delivers truly scalable high yield AlInAs/InGaAs HBT's with both DC and RF characteristics suitable for large-scale, high speed digital circuit applications.

The damage introduced into GaAs/AlGaAs HEMT structures during pattern transfer (O2 plasma etching of the PMGI layer in a trilevel resist mask) or gate mesa etching (CCl2F2/O2 or CH4/H2/Ar etching of GaAs selectively to AlGaAs) has been studied. For etching of the PMGI, the threshold O+ ion energy for damage introduction into the AlGaAs donor layer is ∼200 eV. This energy is a function of the PMGI over-etch time. The use of ECR-RF O2 discharges enhances the PMGI etch rate without creating additional damage to the device. Gate mesa etching produces measurable damage in the underlying AlGaAs at DC negative biases of 125–150V. Substantial hydrogen passivation of the Si dopants in the AlGaAs occurs with the CH4 /H2 /Ar mixture. Recovery of the initial carrier concentration in the damaged HEMT occurs at ∼400°C, provided the maximum ion energies were dept to ≤400 eV. Complete removal of residual AIF3 on the CCl2F2/O2 exposed AlGaAs was obtained after H2O and NH4 OH:H2O rinsing while chlorides were removed by H2O alone.

GaAs p-n junction mesa-diode structures were fabricated so that both n- and p-type layers could be simultaneously exposed to either O2 or H2 discharges. This simulates the ion bombardment during plasma etching with either CCl2F2/O2 or CH4/H2 mixtures. The samples were exposed to 1 mTorr discharges for period of 1–20 min with DC biases of -25 to -400V on the cathode. For O2 ion bombardment, the collector resistance showed only minor (≤10%) increases for biases up to -200 V and more rapid increases thereafter. In our structure, this indicates that bombardment-induced point defects penetrate at least 500 Å of GaAs for ion energies of ≥200eV. The base resistance displayed only a minor increase (∼10%) over the pre-exposure value even for O+ ion energies of 375 eV, due to the very high doping (1020 cm−3 ) in the base. More significant increases in both collector and base resistances were observed for hydrogen ion bombardment due to hydrogen passivation effects. We will give details of this behaviour as a function of ion energy, plasma exposure time and post-treatment annealing temperature.

The wet chemical etching rates of InGaP in H3 PO4:HCL:H2O mixtures have been systematically measured as a function of etch formulation and are most rapid (-1 μm · min−1) for high HCl compositions. The etch rate, R, in a 1:1:1 mixture is thermally activated of the form R ∝ e−Ea/kT, where Ea = 11.25 kCal · mole−1. This is consistent with the etching being reaction-limited at the surface. This etch mixture is selective for InGaP over GaAs. For chlorine-based dry etch mixtures (PCl3 /Ar or CCl2 F2 /Ar) the etching rate of InGaP increases linearly with DC self-bias on the sample, whereas CH4/H2-based mixtures produce slower etch rates. Selectivities of ≥500 for etching GaAs over InGaP are obtained under low bias conditions with PCl3/Ar, but the surface morphologies of InGaP are rough. Both CCl2F2/Ar and CH4/H2/Ar mixtures produce smooth surface morphologies and good (>10) selectivities for etching GaAs over InGaP.

Anisotropie RIE etching of Tungsten (W) in a low voltage CF4 or SF6 plasma while achieving features as small as 0.50 μm is demonstrated using Titanium (Ti) as an etch mask. For reasons of reliability and tolerance to high temperature processing techniques, W can be a desirable contact metal in microelectronics fabrication. Due to its high melting point (3400°C) it is not practical to evaporate W contacts using conventional liftoff photolithography methods. Therefore pattern transfer of sputtered W must be performed by plasma etching using some type of mask. In III-V materials systems, a Fluorine based plasma is desirable due to its high selectivity for W over semiconductor materials. The problem is that when using conventional photoresist masks, W does not etch anisotropically. Therefore critical feature dimensions (which are sub-micron for FET gates) and vertical profiles cannot be successfully transferred to the underlying W. However by using a Ti mask during the CF4 or SF6 plasma etch, TiF4 is produced on the sidewalls of the W inhibiting any horizontal etch. The Ti mask can be removed selectively after etching of the W is complete. Using a Ti mask to etch W ensures excellent pattern transfer of device dimensions even at very low bias voltage.

Magnetron reactive ion etching is an attractive alternative to reactive ion etching since it has the potential for producing minimal surface damage while still retaining the advantages of reactive ion etching. We report here the results of a study of GaAs magnetron ion etching using Freon-12 and silicon tetrachloride etch gases. Differences are found in etch profiles and surface region characteristics of GaAs samples etched by the two gases. The relevant mechanisms are discussed.

Wet chemical gate recessing of GaAs based devices suffers from poor control and uniformity of the recess etch depth. Electrical variability can be particularly severe for heterojunction devices that contain thin highly doped layers. This problem can be addressed by the use of etch stop layers and the appropriate etch chemistry. In this paper, results on the selective plasma etching of GaAs from InGaAs and AIGaAs etch stop layers are presented. Using a BCl3 plasma, GaAs layers were removed from thin lnxGa(1-X)As (0.12<x<0.25) layers with selectivities >1000 to 1 due to the poor volatility of indium chlorides. With the addition of SFe, the etch process becomes selective to AlxGa (1-X)As due to the formation of a non-volatile AlFX layer. By the judicious choice of etch conditions (high pressure and low power resulting in low DC bias and optimal BCl3/SF6 ratio), isotropie etch profiles with minimal substrate damage and GaAs to Al0.25Ga0.75As selectivities >1000 to 1 have been achieved. Using these etch conditions, pseudomorphic HEMT wafers were selectively plasma gate recessed yielding saturated current uniformities across a 3 inch wafer of <±1.0mA/100μm of gate periphery. Device characteristics and uniformities that are dependent upon the material structure and epitaxial layer thickness and dopant uniformities rather than upon the gate recess process are realized.

The effects of selective reactive ion etching (SRIE) in SiCl4/SiF4 plasmas on GaAs/AlxGai-xAs heterostructures have been studied. Auger electron spectroscopy (AES) and Schottky diode measurements were performed to determine the effects of SRIE and post-SRlE processing on the surface conditions of AlGaAs layers. The degradation of the two-dimensional electron gas (2-DEG) properties of GaAs/Al0.3Ga0.7As heterostructures due to low-energy ion bombardment during SRIE were investigated by conducting Hall measurements at 300 and 77 K. Finally, measurements were performed on dry etched GaAs/Al0.3Ga0.7As modulation-doped field effect transistors (MODFETs) to determine the effects of SRIE on transconductance and threshold voltage. It is shown that extensive overetching during gate recessing results in an increase in device threshold voltages.

The fabrication of devices based on III-V materials often requires a number of different reactive ion etching (RIE) processes that must be implemented sequentially. These processes are typically carried out in different RIE systems to avoid cross contamination. In this paper, we describe a multichamber RIE system configured to provide several sequential etch processes required for the fabrication of optoelectronic devices. This system has been used to fabricate InGaAsP/lnP ridge waveguide laser arrays with etched mechanical features that enable passive alignment of the lasers with single-mode fibers. Laser arrays with threshold currents as low as 20 mA have been processed with a high degree of uniformity. This system has also been used to develop a laser facet etch process based on CH4/H2/Ar chemistry. This process has been used to fabricate lasers with monolithically integrated rear facet monitors. These etched facet lasers have threshold currents comparable to lasers with both facets cleaved.

An etch-back polymide planarization process for the emitter contact of AlGaAs/GaAs HBTs using PC-1500 is presented. The degree of surface topography has a major impact on the yield in HBT fabrication. A planarization process using a spin-on sacrificial layer to produce a planar interlevel dielectric layer would be very beneficial in allowing thicker and more uniform emitter contacts therefore enhancing the yield and current handling capability. The PC-1500 polymer flows at 200°C and provides a much better planarity than regular photoresist. For patterns from -3 μm to 250 this polymer can achieve 80% to 92% planarity. The wafers were etched in a parallel plate, single wafer reactive ion-etching system with a mixture of oxygen and Freon-14. The etch rate of this polymer increased with the oxygen content of the discharge then became fairly constant at high O2 concentrations while the etch rate of the underlying dielectric film (SiN) was proportional to the Freon 14 content. This new polymer shows little loading effect. A 1:1 etch rate ratio of SiN to PC-1500 was established for good planarity.

Raman spectroscopy is used to study crystal damage and electrical damage in n+-GaAs produced by reactive ion etching (REE). H2 RIE is compared with CH4/H2 RIE and the effect of temperature annealing is studied. The results are compared with C-V analysis. It is found that structural damage introduced by RIE in the surface layers of the sample is larger for the H2 plasma than for the CH4/H2 plasma. Annealing results in a decrease of this structural damage. H2 RIE as well as CH4/H2 RIE cause an increase of the inactive surface region. This increase is found to be larger for the H2 RDE. C-V experiments show that annealing results in a reactivation and associated decrease of the width of the inactive region.

The damage introduced by CH4/H2 reactive ion etching (RIE) and its recovery after thermal annealing has been investigated by Hall measurements and low temperature photoluminescence (PL) on pseudomorphic AlGaAs/InGaAs modulation doped structures. After plasma exposure, the PL intensity has significantly decreased and shifted in energy. In order to study the recovery of the damage introduced by the plasma, thermal annealing was done at temperatures between 350 and 500°C. We observed that the luminescence emission is totally recovered after annealing at 450°C. Hall measurements at room temperature (RT) and at 77K showed that the electrical characteristics of these structures can be restored only after thermal annealing at 500°C.

The optimised etching conditions have been applied in a fabrication process for submicron dry gate recessed pseudomorphic delta-doped AlGaAs/InGaAs modulation doped field effect transistors (MODFETs). For a 0.25 mm gatelength device the maximum DC transconductance value was as high as 680 mS/mm. The same value was extracted from measurements at 15 GHz.

RIE is an important technique in obtaining anisotropie etch profile. This is a critical requirement for very deep etching which needs long etch duration. Among many factors which affect RIE characteristics in deep etching, the following are most concerned: (1) the etch mask: needs suitable plasma resistance without significant plasma attack for extended etch time; (2) Long time stability in etch rate and surface conditions for the sample; (3) Etch profile: should be anisotropie with tolerable undercut In this work, CCl2F2 and SiCl4 were used with CCl2F2 as the main etchant. Ar was used in the initial stage for sputtering away surface residues prior to actual etching was performed. Three types of etch masks were prepared and their performance such as plasma was investigated. Multilayer metal etch mask has very low etch rate in plasma and its etch rate selectivity is around 300. The etch selectivities of GaAs to Si3N4 and to photoresist are 35 and 23, respectively. Etch mask can be chosen depending on the thickness of etch mask and the required GaAs etch depth. The etch rate of GaAs was found significantly increased when metal mask was applied. While PR mask is easier for inducing surface coating.

Two fundamental requirements for RIE are the formation of nearly volatile etch products and sufficiently high physical bombardment to remove all substances on the surface. In this study, the GaAs wafer was in-situ pretreated with NH3 or CHF3 plasma prior to actual etching process. The main etchants are CCl2F2 and SiCl4. By adding these additives to the main etch gases, the resulting etch performance was significantly affected. For instance, DC self-bias of CCl2F2 plasma is relatively low and can increase with such gas addition, thus the etching properties related to physical bombardment change too. CHF3 improve GaAs etch rate in CCl2F2through increasing concentration of reactive chlorine-containing species. While CHF3 enhance etch rate in SiCl4 plasma. The as etched samples were examined with X-ray photoelectron spectroscopy. Details of the experimental results will be described.

In the self-alignment technology for GaAs MESFET, the pattern technique for refractory suicide gate is needed. Reactive ion etching (RIE) of TaSix on GaAs has been performed in a mixture of CF4 and O2 Etching properties have been studied as function of oxygen percentage, total pressure and power. The samples were then examined in Scanning electron microscopy (SEM) and Auger electron spectroscopy (AES) to understand the surface morphology and constitution. It is found that the etch rate of TaSixincreased with increasing oxygen percentage initially, reached a maximum value near 10∼15% O2, then started to decrease with increasing oxygen at applied power 100 watt, pressure 50 mtorr, and total gas flow 40 seem. This etch rate also increases with RF power and total pressure in CF4 + O2 15% gas at gas flow rate 40 sccm. For GaAs etching, the rate is independent of oxygen percentage. This etch rate of GaAs also increases with power, but decreases with total pressure. Meanwhile, the SEM micrograph shows no undercut for sample after RIE at the applied power 140 watt with the pressure of 20 mtorr.

A novel electron cyclotron resonance (ECR) reactor for plasma processing of III-V compound semiconductors is presented. The reactor is appropriate for processes which are damage sensitive or for applications in which direct overhead access to the wafer is advantageous. The reactor uses an axisymmetric magnetic geometry provided by electromagnets and locates the source region below the wafer; there is no direct line of sight to the wafer from the plasma discharge region. The geometry allows more flexible neutral gas handling capabilities and frees the area above the wafer for diagnostics, neutral gas manifolds, energetic ion beam injection, laser irradiation of the wafer or vacuum pumping access. The combination of auxiliary processing with beams or laser light simultaneous with the plasma processing step opens possibilities for new processes, increased throughput and reduced wafer handling.

The viability of forming an ohmic contact to InGaAs/InP structures by means of a load-locked RT-LP(MO)CVD integrated process, was demonstrated. The wafer was loaded into the reactor chamber and was exposed to a sequence of dry and in-situ processes which led to the formation of an ohmic contact. After an in-situ cleaning of the wafer through a thermal cycle at 500°C under a flow of tertiarybutylphosphine (TBP), which provided the needed free hydrogen for a mild etching of the surface, however with an over pressure of P to eliminate surface degradation, a layer of silicon oxide (SiOx ) was rapid thermal chemical vapor deposited (RT-CVD) onto the InGaAs/InP sample via a rapid thermal cycle (500°C,30 s) in a low pressure O2 and 2% diluted SiH4. Dry etching of 50–150 μm wide contact stripes was carried out using a contact stencil mask by an electron-cyclotron resonance (ECR) dry etching. Subsequently the wafer was reloaded through the load-lock to the main chamber and a TiNx layer were selectively deposited into the via-holes and processed to provide an ohmic contact to the InGaAs/InP substrate. Finally, a blanket deposition of conducting cap layer was realized by means of RT-LP(MO)CVD. This work provides a solid demonstration to the feasibility of the single-wafer-integrated-process (SWIP) as an approach to replace the batch process traditionally used for manufacturing the InP-based optoelectronic devices.

The use of wet-chemical removal of native oxide in a sealed nitrogen ambient prior to deposition of metal on GaAs is shown to be an effective method of engineering the Schottky barrier height of the metal contacts. Due to its higher metal work function, a barrier height of 0.98 eV for Pt on n-type GaAs is demonstrated. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV). MESFETs fabricated using PtAu bilayer contacts show reverse currents an order of magnitude lower than TiPtAu contacted companion devices, higher reverse breakdown voltages and much lower gate leakage. Utilizing this technology of oxide removal and the PtAu bilayer contact provides a much simpler method of enhancing the barrier height on n-type GaAs than other techniques such as counter-doping the near-surface or inserting an interfacial layer.