The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and processing cost is increasing dramatically. When interconnect feature size decreases and clock frequencies increase, RC time delays become the major limitation in achieving high circuit speeds. The miniaturization of interconnect feature size also severely penalizes the overall performance of the interconnect, such as increasing interconnect resistance and interconnect current densities, which lead to reliability concerns due to electromigration. Lower resistance metal and lower dielectric materials are being considered to replace current Al and SiO2 interconnect materials. Innovative efforts in circuit design, process development, and the implementation of new materials can provide solutions. This issue of the MRS Bulletin focuses on the industrial viewpoint of copper interconnects. (A previous issue of the MRS Bulletin, June 1993, addressed university research approaches to copper metallization.) Articles in this issue, from six major semiconductor companies—IBM, Motorola, AT&T Bell Laboratories, SEMATECH/National Semiconductor, NTT, and Fujitsu—provide a real-world viewpoint of the challenges faced when replacing aluminum with copper. The articles published in both issues also contain a comprehensive list of references (more than 300) to articles, patents, and device applications related to copper metallization for ULSI applications.

Significant progress has been made in building multilevel copper interconnection systems for advanced microelectronics. In this article, we examine some of the materials science issues underlying this progress, and indicate where significant materials challenges remain. It is probable that several approaches to process integration will be developed for copper interconnections, as has been the case with aluminum systems. The first successful demonstration of a fully integrated 4-level copper/polyimide (Cu/PI) interconnection system has been described by Luther et al. of IBM. A schematic cross section of this interconnection system is shown in Figure 1, indicating multiple layers of BPDA-PDA polyimide (PI 5810), Cu lines and studs, and layers of Ta and Si3N4 which serve as diffusion barriers, adhesion layers, and stopping layers in the patterning and planarization processes. This system demonstrates excellent planarity, as shown in the SEM cross section in Figure 2. The electromigration lifetime of this Cu/PI system is greatly improved relative to state-of-the-art aluminum-based systems, and the dielectric integrity appears adequate. Signal propagation studies also confirm the performance improvements anticipated for copper as a low-resistivity conductor and the use of Cu may allow significant capacitance reduction (≃ 25%) simply by scaling Cu lines to equal the resistance of Al lines. In parallel with efforts to introduce Cu metallization for its low resistivity, extensive efforts are under way to replace SiO2 with lower dielectric constant insulators.

The Semiconductor Industry Association (SIA) roadmap calls for the incorporation of Cu plugs (vias) integrated with interconnects in 1997. Copper is being evaluated for ULSI metallization because of its lower bulk electrical resistivity and its superior resistance to electromigration and stress voiding as compared to commonly used aluminum and its alloys. One of the major drawbacks of Cu is its fast diffusion in Si and drift in SiO2-based dielectrics, resulting in the deterioration of devices at low temperatures. Hence a diffusion barrier is necessary between Cu and Si or SiO2. Figure 1 is a cross section of

a three metal level interconnect structure using Cu as the conductive material. The interlevel dielectrics (ILD) could be conventional SiO2-based materials or more ideally, materials with low dielectric constants such as polyimide. If conventional SiO2 is used, then Cu plugs and interconnects have to be enclosed in diffusion/drift barriers so that Cu will not move into Si or SiO2 under thermal stress or biased temperature stress (BTS).

This article reviews the published studies on conductive diffusion barriers between thin Cu films and Si substrates. In addition, the work on diffusion and drift of Cu into commonly used inorganic dielectric systems is also summarized. Finally, some concerns involving diffusion/drift barriers between Cu and Si or SiO2 for sub-0.5 μm feature size with high aspect ratios are discussed.

In the microelectronics industry, integrated circuit (IC) device performance is continually increasing while the critical feature sizes are rapidly decreasing. Since this trend is expected to continue for future generations of ICs, areal density constraints often require that circuit designs utilize multilevel structures with vertical interconnects. It was recently demonstrated that the resistivity of the metal interconnects may limit device performance in multilevel thin-film structures. Although Al metallurgy (Al/2 wt.% Cu alloy) is extensively used for IC metallization today, lower resistivity metals, such as gold, copper, and silver may be necessary for designs requiring feature sizes of 0.25 μm or less. Chemical vapor deposition (CVD) is an attractive technique for the conformal filling of submicron vertical interconnects. For CVD to be generally applicable to IC fabrication, volatile precursors with adequate stability must be designed and optimized. Lastly, IC metallization typically requires that both uniformity and conformality be achieved simultaneously in a single process step.

Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density, and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.18 μm, while microprocessors will pack more than 15 million transistors over an area ~700 mm. To conserve area, interconnects will continue to be stacked at an increasing number of levels (six by the year 2000, versus four in today's leading microprocessors), and the minimum spacing and width within an interconnect layer will shrink to 0.3 μm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures.

Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused on means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations or by the development of complicated multimetal stacks. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7 μΩ cm for Cu versus 3.0 μΩ cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (~1100°C versus ~600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration.

Chemical plating techniques have been used in silicon processing for many years for junction delineation and ohmic contact formation. In recent years, interest in this area has been renewed because of the potential use of electroless copper deposition for ultra-large-scale integration (ULSI) metallization and for the formation of thin metal etch masks for deep-ultraviolet lithography. Good deposition selectivity, low operating temperature, high copper purity, good filling characteristics, and planar topography have been among the many advantageous attributes reported from early investigations.

In the June 1993 issue of the MRS Bulletin on Copper Metallization, Cho et al. gave an exposition on the use of electroless copper for VLSI. More comprehensive reviews of the electrochemical fundamentals can be found in References 8,9, and 10. This article summarizes the current understanding of various chemical and material aspects of this deposition method in an attempt to give an overview of the film growth characteristics for thin film applications. Because of length limitations, only selected topics are included. The emphasis is on the initiation conditions and the resultant microstructure and properties obtained. We also discuss special considerations for fine pattern formation.

The information presented here applies primarily to electroless copper deposition on metals and metal silicides since these are the typical substrate surfaces for metallization in contact vias of ULSI circuits. Strictly speaking, metallization of upper-level interconnects occurs mostly on a dielectric base. However, since copper systems usually require a diffusion barrier to shield the copper from diffusing into the silicon, we can treat the deposition process startingfrom this layer onward.

As the degree of large-scale integration (LSI) increases, the area of a single transistor will diminish and the density of transistors will increase. Accordingly, technology for high-density wiring to interconnect the huge number of transistors is needed because transistors cannot perform any useful functions without interconnects and electrodes. For advanced microprocessor chips with a sub-half-micron design rule and at least four interconnect layers, the minimum width of the interconnects becomes less than 0.35 μm.

Aluminum or an aluminum alloy is now generally used as the interconnect material in LSI circuits because the physical and chemical properties of aluminum are compatible with current LSI processing: Aluminum forms a thin protective oxide film that withstands various thermal processes; it has relatively low electrical resistivity and halide compounds with a relatively high vapor pressure which are suitable for reactive ion etching (RIE), and it is an inexpensive material. The reliability of aluminum interconnects, however, is a major concern for maintaining the total reliability of advanced LSI. Because of its relatively low melting point, aluminum as an interconnect material is susceptible to stress- and electromigration, which leads to open failure of the interconnect. It is well-known that these failure modes are accelerated by decreasing the width and thickness of the interconnects. Hence, use of aluminum interconnects may be limited for future sub-half-micron LSIs.

Investment in high-performance and large-scale integration (LSI) has been increasing and low-cost fabrication equipment, simple processing, and short turnaround are big concerns. The propagation delay time in a device is reduced with a reduction in device size, and wiring delay becomes longer than device delays. Wiring then has become as important as the device itself. Future multilevel wiring will require five to seven levels. The multilayer wiring itself will not be easy to achieve, because of increased wiring cost, process complexity, and longer turnaround. We must overcome these problems.

The materials required for wiring so that ULSI performance and reliability in RISC (reduced instruction set computer), and CISC (complex instruction set computer) type processors and DSPs (digital signal processors) can be increased must have a lower resistivity and higher resistance to electromigration (EM) and stress migration (SM) than do aluminum alloys. Gold, copper, and silver are candidate wiring materials. Copper is especially attractive, but we must overcome several obstacles to take advantage of its potential.

This article will discuss wring and via resistance delay, Cu CVD technology, the surface reaction mechanism, copper patterning technology, copper oxidation and diffusion prevention, and copper wiring reliability.

Multilevel metallization is becoming an increasingly interesting area of research as circuit fabrication technologies are scaled down to deep submicron dimensions. The mainstream of today's interconnection technology is AlSiCu metallization. Al-based solutions, however, seem to be limited in resistivity as well as in electromigration performance. Because of its low electrical resistivity and its resistance to electromigration, copper is considered to be a promising new solution for on-chip interconnections. The performance of copper would allow its use in wiring with very small linewidths, as required for ULSI circuits. Before considering copper metallization in ULSI processing, however, major problems still have to be overcome.

Taking into account these considerations, a European project is now devoted to the evaluation of copper-based metallization for ULSI applications. The project, Copper Interconnection (COIN), associates the efforts of seven European partners.

The objectives of COIN are to evaluate and develop a set of optimized solutions which demonstrate to our industrial partners the interest of using on-chip copper metallization. High deposition rates, low temperature processing, thermal stability, reliability, and low cost are the main goals.

The COIN project is devoted to an exploratory study concerning the major issues to be addressed in order to reach the above targets. The choice is to limit, for as long as possible, the modifications of existing multilevel metallization (MLM) structures to a simple replacement of the aluminum by copper interconnection levels. The refractory metal layers in MLM structures (TiSi2, Ti, TiN, W) will be maintained in the copper metallization scheme as will the use of SiO2 as the dielectric material. Another consideration in our approach is the possibility of achieving this substitution with minimum modification to existing fabrication lines. Thus, processes for copper deposition and copper patterning will be developed using existing machines and machine concepts for as long as possible.