Single-ended and balanced 90–120 GHz microstrip power amplifier MMICs have been designed for cost-sensitive 5G and 6G backhaul in a commercial 6-inch, 0.1-µm GaAs process. At 108 GHz, measured output power is 20.4 and 22.5 dBm, respectively. At 120 GHz, measured output is 12.6 and 17.4 dBm, respectively. This is the highest reported for GaAs, among the highest reported to date for microstrip MMIC amplifiers at these frequencies and competitive with more expensive InP and GaN processes. Measurement is compared with simulation.

In this paper, two high efficiency monolithic microwave integrated circuits (MMICs) are demonstrated using NANOTAM's in-house Ka-band fabrication technology. AlGaN/GaN HEMTs with 0.2 ${\rm \mu}$m gate lengths are characterized, and an output power density of 2.9 W/mm is achieved at 35 GHz. A three-stage driver amplifier MMIC is designed, which has a measured gain higher than 19.3 dB across the frequency band of 33–36 GHz. The driver amplifier exhibits 31.9 dB output power and 26.5% power-added efficiency (PAE) at 35 GHz using 20 V supply voltage with 30% duty cycle. Another two-stage MMIC is realized as a power amplifier with a total output gate periphery of 1.8 mm. The output power and PAE of the power amplifier are measured as 3.91 W and 26.3%, respectively, at 35 GHz using 20 V supply voltage with 30% duty cycle. The high efficiency MMICs presented in this paper exhibit the capabilities of NANOTAM's 0.2 $\rm\mu$m AlGaN/GaN on SiC technology.

Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

This paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

This paper presents the design approach and test results of a full passive, decade bandwidth GaAs MMIC, composed by a phase shifter (PS) with a cascaded absorptive single pole double throw switch, suitable for transmitter/receiver modules in active electronically scanned array. The proposed PS – fabricated using a UMS GaAs 0.25 PHEMT process – combines all-pass filters with high-pass filters, in order to provide less than 13 dB insertion loss, less than ±20° phase error and less than ±2.5 dB amplitude error in the 0.8–8 GHz bandwidth.

This paper reports on digital transmitter architecture for the 450 MHz band using an envelope delta-sigma modulator realized in CMOS and a voltage-mode class-S (VMCS) power amplifier (PA) based on GaN monolithic microwave integrated circuits (MMICs). The class-S PA is characterized for narrowband single-tone signals and a single- as well as a four-carrier downlink wideband code division multiple access (WCDMA) signal with a peak-to-average power ratio of 7.5 dB. Using single-tone excitation the PA shows a maximum drain efficiency of 86% and a peak output power of 4.4 W. At 6 and 10 dB back-off, 59 and 36% efficiency are achieved, respectively. With the single- and four-carrier WCDMA input signals maximum drain efficiencies of 64 and 53% are reached, respectively, and peak output power is 0.7 W. The adjacent channel leakage ratio shows values of about −34 dBc (5 MHz) and −38 dBc (10 MHz) for single-carrier WCDMA excitation. This is the first complete VMCS PA chain characterized with standard communication signals.

In this paper we present the design and realization of a high-power amplifier in grounded coplanar transmission line technology using AlGaN/GaN dual-gate High electron mobility transistors (HEMTs) with a gate-length of 100 nm to achieve a high gain per stage and high output power. A large-signal model was extracted for the dual-gate HEMT based on the state-space approach. For the fabricated dual-stage amplifier a continuous-wave saturatedoutput power of up to 24.8 dBm (0.84 W/mm) was measured at 63 GHz for 20 V drain bias. A small-signal gain of more than 20 dB was achieved between 56 and 65 GHz.

We report cryogenic noise temperature and gain measurements of a prototype heterodyne receiver module designed to operate in the atmospheric window centered on 150 GHz. The module utilizes monolithic microwave integrated circuit (MMIC) InP high electron mobility transistor (HEMT) amplifiers, a second harmonic mixer, and bandpass filters. Swept local oscillator (LO) measurements show an average gain of 22 dB and an average noise temperature of 87 K over a 40 GHz band from 140 to 180 GHz when the module is cooled to 22 K. A spot noise temperature of 58 K was measured at 166 GHz and is a record for cryogenic noise from HEMT amplifiers at this frequency. Intermediate frequency (IF) sweep measurements show a 20 GHz IF band with less than 94 K receiver noise temperature for a fixed LO of 83 GHz. The compact housing features a split-block design that facilitates quick assembly and a condensed arrangement of the MMIC components and bias circuitry. DC feedthroughs and nano-miniature connectors also contribute to the compact design, so that the dimensions of the moduleare approximately 2.5 cm per side.

This work describes the integration of Schottky diodes into fast GaN MMIC process technology suitable for the realization of switch-mode power amplifier core chips for class-S operation at 2 GHz. With the demonstration of this technology, the so-called third-quadrant issue, which reduces the efficiency in band pass-Δ-Σ class-S operation can be diminished on device level. Compared to a hybrid diode assembly, the broadband properties of the amplifier module with on-chip-integrated diode can be improved by the reduction of parasitic losses. The GaN heterostructure field effect transistors (HFETs) with integrated series diode show a cut-off frequency of 28 GHz with drain breakdown voltages exceeding −100 and +100 V and comparable large signal performance to conventional GaN HFETs at 10 GHz. MMIC core chips for class-D and class-S switch-mode power amplifier modules are demonstrated for the operation at mobile communication frequencies between 0.45 and 2 GHz and signal bit rates up to 8 Gbps. The circuits yield broadband output power levels between 4 and 9 W with efficiencies of up to 80%.

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

The design, realization, and characterization of highly efficient powerbars and monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs) with AlGaN/GaN high electronic mobility transistors (HEMTs) are presented for the frequency range between 1 and 30 GHz. Packaged powerbars for the frequency range between 1 and 6 GHz have been developed based on a process called GaN50 with a gate length of 0.5 μm. Based on a GaN25 process with a gate length of 0.25 μm, high-power MMIC amplifiers are presented starting from 6 GHz up to advanced X-band amplifiers and robust LNAs in microstrip transmission line technology.

The present paper presents an overview of the AlGaN/GaN-based circuits realized over the years. Two technological processes with 0.25 and 0.7 μm gate length allowed one to address applications from L- to Ku-bands. Depending on the process development and frequency of the operation, results on hybrid or MMIC technology are presented. GaN technology is evaluated through the realization of high-power amplifiers, robust low-noise amplifiers, or power switches to prepare the next generation of Tx-Rx modules.

We present an overview on epitaxial growth, processing technology, device performance, and reliability of our GaN high electron mobility transistors (HEMTs) manufactured on 3- and 4-in. SiC substrates. Epitaxy and processing are optimized for both performance and reliability. We use three different gate lengths, namely 500 nm for 1–6 GHz applications, 250 nm for devices between 6 and 18 GHz, and 150 nm for higher frequencies. The developed HEMTs demonstrate excellent high-voltage stability, high power performance, and large DC to RF conversion efficiencies for all gate lengths. On large gate width devices for base station applications, an output power beyond 125 W is achieved with a power added efficiency around 60% and a linear gain around 16 dB. Reliability is tested both under DC and RF conditions with supply voltage of 50 and 30 V for 500 and 250 nm gates, respectively. DC tests on HEMT devices return a drain current change of just about 10% under IDQ conditions. Under RF stress the observed change in output power density is below 0.2 dB after more than 1000 h for both gate length technologies.

GaN technology has gained a lot of attention in Europe over the last few years for various domains including RF electronics. After a few years of active observation, United Monolithic Semiconductors (UMS) has taken the decision to introduce a GaN technology family in its portfolio. Based on its extensive experience of III–V technology and the intensive support and collaboration with partners and European research institutes, UMS has developed the capability to produce state-of-the-art GaN devices and circuits. The present paper will summarize the current status achieved and illustrate it with a few representative examples. Aspects covering material, devices, and circuits will be addressed.

The use of 130-nm CMOS for power amplifiers at 20 GHz is explored through a set of power amplifiers as well as transistor level measurements. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, and the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor-level characterization using load pull measurements on 1-mm gate width transistors yielded 148-mW/mm output power. Transistor modeling and layout for power amplifiers are also discussed. An estimate on the maximum achievable output at 20 GHz from 130-nm CMOS power amplifiers, based on findings in this paper and the literature, is finally presented.