The deformation characteristics of continuous thin Cu films 0.3-1.0 μm thick on Si substrates with Si3N4 diffusion barriers and passivations have been investigated using substrate curvature and x-ray diffraction methods at room temperature and at temperatures up to 600°C. The stress levels at all temperatures were modelled on the basis of deformation mechanisms used to describe bulk Cu and using mechanisms and model modifications specific to thin films. The Cu films were found to support high stresses at room temperature which depended strongly on the film thickness and presence of a passivation. These stress levels could be adequately modelled by considering both dimensional and microstructural constraints on the glide motion of dislocations. At higher temperatures, the presence of a passivation was seen to change the stress levels reached in a film by one to two orders of magnitude. For unpassivated Cu films, a model based on power law creep could accurately describe stress-temperature data. For passivated films, the addition of a threshold stress to the power law model provides substantial agreement between model and measured data. Exposure of Cu films to small amounts of air or oxygen has a significant effect on thermomechanical behavior. The deformation behavior of differently oriented grains in the films were observed to be quite different from one another. Cu films behave neither like bulk Cu nor like Al thin films. A priori prediction of stress levels in Cu films or patterned structures for use in reliability calculations is not possible at this time.

For BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very important to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length = 800μ, thickness = 0.7μ, widths = 1, 5, 10 μ) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si3N4, was used as passivation. DC stress was performed at 175, 200, and 225°C. Microbeam X-ray Diffraction (μ XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.

The electromigration performance of samples fabricated with new Al via-filling techniques are studied and compared. The new techniques are (1) Hot Al mono-chamber and (2) CVD/PVD Al. Their electromigration performances are assessed over a range of stress conditions and compared with that of a standard W- etchback technique.

Internal stresses inevitably arise in integrated microstructures. This paper reviews a fracture mechanics approach to devising design rules to avert cracking. The smallness of the feature size permits a strategy different from that conventionally used to analyze the fracture of bulk materials. In an integrated microstructure, high tensile stress is localized in small regions. The elastic energy stored in each region scales with its volume. The surface energy associated with the creation of a crack scales with the surface area of the crack. Thermodynamics dictates that a flaw cannot grow if the stored elastic energy is lower than the created surface energy. Consequently, for a sufficiently small feature size, the volume-to-area ratio is small, and no flaw can grow. Our design rules do not depend on flaw size. They are deterministic, and rely on well-specified geometric and physical parameters. Furthermore, the stress singularity at corners does not cause any particular difficulty. As an example, the thermal misfit cracking in a multilevel interconnect test structure is investigated.

Microhardness testing is widely used for characterizing the mechanical properties of both bulk materials and thin films. Although this technique is usually associated with hardness measurements, fracture properties of brittle materials can also be studied with cracking associated with microhardness indentations. It is well known that the length of radial cracks emanating from the comers of indents made with Vickers and Berkovich indenters is related to the fracture toughness of the material. In the present study, microhardness testing has been used to follow the evolution of the mechanical properties of a 10 nm.Cu/200 nm. Ni(V)/300 nm. Al(Cu) thin film deposited on a Si substrate. Composite hardness and fracture toughness have been followed as a function of heat treatment temperatures and times and were found to be dependent on both variables. The roles of residual stresses, interdiffusion, and intermediate phase formation in the observed variation in hardness and fracture toughness are discussed.

A technique for the measurement of brittle thin film toughness has been developed. It is based on the mechanics of channel cracking in thin films. Dielectric films including CVD silicon oxide and silicon nitride films were studied using this technique. To prevent channel cracks from propagating into silicon substrates, an aluminum layer was deposited prior to the deposition of the dielectric layer. By using a specially made bending fixture, the cracks were observed in situ when the samples were subject to well controlled stresses. It was observed that for each film, a well defined critical film stress level existed, beyond which the crack velocity accelerated very rapidly. The critical film stresses were obtained by superposition of the critical applied stresses and the residual stresses in the films due to deposition and thermal expansion mismatch. It was shown that this technique was highly consistent in critical stress measurement. A simple shear-lag model was used to obtain the film toughness values using the measured critical film stress data.

The metallization of Si represents a important industrial process and produces a bi-layered composite of a ductile metal film on a brittle substrate. The mechanical properties of such a composite are determined by the properties of the two layers and the interface and influenced by the fact that the metallized layer, being a very thin film, possesses properties different from those of a bulk material. The fracture toughness is also influenced by the nature and distribution of defects which may be generated during use of these materials, even if the manufacturing process produces a reasonably defect free material. Indentation cracking has been extensively used for the measurement of fracture toughness due to its small sample size requirements as well as a relatively good correlation with values obtained from traditional fracture mechanics tests. The indentation process, with its associated cracks, produces permanent plastic deformation and also introduces a residual stress field. This field influences the crack pattern generated in an adjacent indent and can be used as a methodology to model the influence of multiple defect sources.

The present study was aimed at understanding the effect of a thin Ti alloy metallization layer sputtered on a Si wafer on the sizes of the cracks associated with the indents. It was also aimed at studying the interaction between cracks emanating from sequentially placed indentations. The distance between the indents which generated these cracks was varied from a level comparable to the crack size to a level where interaction could be ignored. This paper discusses the changes in the nature as well as the sizes of cracks due to the presence of the metallization layer as well as the interaction between the stress fields of the indents in this ductile thin film – brittle substrate composite and possible methodologies for delineating these effects.

Following the general tendency of downsizing in microelectronic packages, the interposing layer between silicon chip and organic board is constantly reduced while the differences in thermal expansion stay constant. Consequently, thermal stresses have become the most important reliability concern in advanced packages. Finite element analysis is known as an effective way of theoretically studying the mechanical situation in multi-component systems with complex material behavior. The paper presents results of finite element simulations that provide practical guidance for design, process and material developments of chip size packaging (CSP), flip chip (FC), and direct chip attach (DCA) modules. Using realistic and efficient models, a low-cost CSP concept is assessed, the effects of underfill, underfill imperfections, and underfill defects on the reliability of FC modules are studied, and an optimum set of mechanical properties for underfill materials is proposed. Finally, reliability risk factors in DCA modules are identified and preliminary design guidelines are given.

Thermal fatigue of flip-chip solder joints between a chip and chip carrier is a serious reliability concern. Differences in the temperature and/or in the coefficients of thermal expansion between the chip and substrate lead to stresses which may result in fatigue damage and eventual failure of the interconnect. Conventionally, the solder lives have been estimated by a Coffin-Manson type relation. However, this largely empirical approach becomes inadequate when comparing thermal histories that are widely different, as in the cases of accelerated thermal cycling and power cycling. In this study, we use a damage integral approach where the fatigue damage rate is calculated based on the momentary stress and strain (estimated analytically) experienced by the solder joints. The momentary damage is then integrated over the entire loading history to yield total damage at any moment.