Direct patterning of a semiconductor surface to produce an ultrathin oxide mask has proven to be a promising approach for integrating lithographic methods based on scanned probe microscopy (SPM) into existing electronics device processing. The resulting masks are capable of withstanding the necessary etching and thermal cycling required for pattern development. Recent work has validated the concept for the fabrication of silicon devices. The current challenges which face this active research area will now require a detailed, predictive understanding of the mechanism responsible for oxidation within an SPM junction in order for the process to optimized with respect to write speed, resolution, and reliability.

The drive to increasingly higher density ultra-large-scale-integration (ULSI) (of electronic circuits) is fuelled primarily by cost; on-chip interconnects are far cheaper than the less dense offchip interconnects. At the same time the escalating cost of an IC factory (‘fab’) is making headlines as it goes through $1B and a large part of this escalation is the cost of high performance lithography tools. The lithographic technology to go below 0.1μm will almost certainly be very different from an extension of today's optical projection and the cost of replacing today's technology will be enormous. A second drawback to higher density is the resistance of narrow interconnects. As a result some people have suggested that this situation is analogous to that of airliner speed which increased over a period of thirty years from about 100 mph to close to 600 mph but has not increased in the last 35 years. Still faster speed was technically possible, and hence was pursued by the military, but is uneconomical for most commercial use. Current technology might take us to 0.1μm which will probably be state of the art 10 years hence so technologies for replacing optical lithography e.g. scanned arrays of proximal probes should be researched now. Other challenges include how to achieve useful interconnect networks employing 50 nm features.

We show how the imaging process in proximity X-ray lithography is capable of reaching the sub-100 nm range. However, The use of proximity X-ray lithography is dependent on the mask to form the correct image of the pattern. The joint development of electron beam lithography patterning tools with high-placement accuracy, of a better understanding of the mask mechanical response and of new aligners, clearly indicates that the goal of using X-ray lithography for nanolithography applications is reachable.

The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.

Patterning on the 10 Å size scale has been achieved with a UHV-STM for Si(100)-2×1:H surfaces. Hydrogen passivation serves as a monolayer resist which the STM locally desorbs, exposing clean Si(100)-2×1 for selective chemistry. Two mechanisms have been identified for hydrogen removal by STM electrons: in the field emission regime direct electron stimulated desorption of hydrogen occurs whereas, in the lower energy tunneling regime, hydrogen desorption results from vibrational excitation of the Si-H bond at high tunneling currents. Furthermore, we find that atomic hydrogen is liberated in contrast to molecular hydrogen evolved during thermal desorption. Selective oxidation and nitridation of the STM-patterned areas has been achieved.