Ohmic behavior is observed in electroless Au contacts to p -type Hg1−xCdxTe. Our investigation of the interfacial chemistry of such contacts suggest that this ohmic behavior may be due to the presence of a Te,O, and CI layer. To verify this correlation with interfacial chemistry, thin plasma oxide layers were used in evaporated Au contacts. The annealed plasma oxidized contacts exhibited low contact resistances. This behavior was attributed to a low interface state density at the interfacial layer/Hg1−xCdxTe interface. In comparison, as-deposited and annealed Au contacts without a thin interfacial layer were rectifying with a large barrier height.

Titanium diboride is an interesting new candidate for VLSI interconnection applications due to its high electrical conductivity and its excellent chemical inertness at high temperatures.

A thermodynamic analysis of the chemical vapor deposition of TiB2 from gaseous mixtures of TiCl4, B2H6 and H2 onto silicon or SiO2 substrates was performed using the SOLGASMIX computer program. Results indicate that at an input gas ratio corresponding to stoichiometry, TiB2 should form in the solid phase. For non-stoichiometric input gas mixtures, other solid phases, including oxides and silicides, are expected to result from the reaction with the Si or SiO2 substrate. Both the addition of hydrogen to the system and increased deposition temperature are expected to enhance the deposition efficiency of TiB2.

Thin films of TiB2, 50 – 120 nm thick, were experimentally deposited on thermally grown SiO2 by low pressure CVD using various gas mixtures in the temperature range 400 – 700°C. Depth profiling of the deposited films, using XPS and RBS, indicated the successful growth of a uniform, stoichiometric TiB2 film. After deposition, the films were rapid thermal annealed at various temperatures in an effort to reduce their resistivity. Resistivity was reduced by 80 % after an 1150°C, 10 sec RTA in Ar to a value as low as 40μΩ-cm, only 4 times larger than that reported for hot pressed polycrystalline TiB2. X-ray diffraction of as-deposited samples showed no crystalline peaks; however, annealed films exhibited the expected TiB2 peaks as well as those of Ti3O5 and TiO2. The titanium oxide was most likely produced during annealing due to trace amounts of oxygen in the Ar atmosphere. The average grain size measured 0.1μm via TEM. More careful control of growth and annealing conditions is expected to result in even lower resistivity TiB2 films.

Using an in-situ stress measurement technique that measures stress as a function of annealing temperature, instabilities in mechanical stress induced by heat treatment in a variety of doped/undoped SiO2 films deposited by APCVD, LPCVD and PECVD techniques have been investigated. A large hysteresis in mechanical stress, caused by first heat treatment to which the as-deposited films are subjected, has been observed in films deposited by APCVD/LPCVD techniques. No such hysteresis is obsesrved in films deposited by PECVD technique. Hysteresis in APCVD/LPCVD films is found to vanish once the films are heat treated at or above 800°C. The results are discussed in terms of oxide densification, the presence of hydrogenous species, and phosphorous.

Electrical properties, metallurgical properties and their relationship of PtSix/GaAs formed by sputter deposition and TiSix/GaAs formed by e-gun multilayer evaporation have been studied. It has been found that TiSix/GaAs contacts exhibit excellent Schottky electrical propcrties and good metallurgical stability after RTA (975°C , 12 sec) but some interface unstability and degradation of electrical properties after conventional FA (800°C ,20 min). The electrical and metallurgical properties of PtSix/GaAs contacts begin to degrate after annealed at 500°C.

An intensive comparison between the efficiency of InP rapid thermal annealing within two types of SiC-coated graphite susceptors and by using the more conventional proximity approach, in providing degradation-free substrate surface morphology, was carried out. The superiority of annealing within a susccptor was clearly demonstrated through the evaluation of AuGe contact performance to carbon-implanted InP substrates, which were annealed to activate the implants prior to the metallization. The susceptor annealing provided better protection against edge degradation, slip formation and better surface morphology, due to the elimination of P outdiffusion and pit formation. The two SiC-coated susceptors that were evaluated differ from each other in their geometry. The first type must be charged with the group V species prior to any annealing cycle. Under the optimum charging conditions, effective surface protection was provided only to one anneal (750°C, 10s) of InP before charging was necessary. The second contained reservoirs for provision of the group V element partial pressure, enabled high temperature annealing at the InP without the need for continual recharging of the susceptor. Thus, one has the ability to subsequentially anneal a lot of InP wafers at high temperatures without inducing any surface deterioration.

The use of AuBe-In/Ag/Au p-ohmic contacts for the base layer of GaAs-AIGaAs heterojunction bipolar transistors (HBTs) is described. Annealing at 420°C for 20 sec produces a contact resistivity of 0.095 Ω mm and a specific contact resistance of l.5 × 10-7 Ω cm2, and the surface morphology of the contact is excellent. The role of the silver is as a diffusion barrier to prevent Au spiking into the base layer which could degrade the HBT performance. The presence of the In layer is highly desirable in order to reduce the contact resistance, probably by forming an InGaAs phase at the metal-GaAs interface. Beryllium acts as the p-type dopant, and the top Au layer is used to lower the contact sheet resistance. Current transport through the structure is dominated by tunneling through the barrier due to field emission in the highly doped base layer at p-type doping levels above ∼1019 cm−3

A multilayer metallization structure in a gate array circuit has been investigated by cross-sectional transmission electron microscopy. Microstructures of thin films, interfaces, contacts, dislocations and step coverage are revealed. Good step coverage was observed when polyimide was used as an insulator between two metal layers.

The incorporation of thin C- or Zn-doped layers under metal Schottky contacts on n-type GaAs can lead to significant enhancements in the effective barrier height. A single C δ-doped layer (p = 1.3 × 1020 cm–3) within 100 Å of the surface leads to a barrier height of ∼0.9 eV, a significant increase over the value for a control sample (∼0.75 eV). The use of two sequential δ-doped layers can lead either to a further enhancement in barrier height, or a decrease depending on whether these layers are fully depleted at zero applied bias. The temperature dependence of current conduction in barrier-enhanced diodes was measured. Both the ideality factor and breakdown voltage degrade with increasing temperature. Zinc δ-doping in a similar fashion produces barrier heights of 0.81 eV for one spike and 0.95 eV for two spikes.

Confirming the results obtained for Ti-Co bilayers on Si and in accordance with the phase diagram, the high temperature formation and stability of three ternary silicides Ti0.75Co0.25Si2 (T phase), TiCoSi (E) and Ti4Co4Si7 (V) is reported. The Si rich T phase grows for Ti / CoSi2 and Co / TiSi2 structures. The tetragonal V compound is obtained by annealing Ti (400 Å) / Co (250 Å) / Si (900 Å) / SiO2 whereas orthorhombic TiCoSi is prepared using Ti / CoSi / Si3N4 samples.

Formation of CoSi2 using the technique of ion implantation through metal (ITM) and subsequent appropriate rapid thermal annealing is described. Silicide morphology is investigated by SEM and TEM. SIMS and RBS are used to determine dopant distribution and junction depth. Self-aligned CoSi2/n+p diodes produced in this technique are presented.

Defect location and identification in the metallization systems of ultra-large-scale integrated (ULSI) devices is becoming increasingly important because of the demands of high device density. An understanding of the sources of defects is crucial to the fabrication of submicron devices. Typically, defect identification is accomplished by electrically testing large metal combs and serpents followed by scanning electron microscopy (SEM) investigation. In order to identify metallization defects quickly, we have fabricated a novel device that bypasses the need to electrically probe. This technique utilizes voltage contrast imaging in-situ SEM to locate defects typically found during ULSI device fabrication. While voltage contrast imaging has been used to locate defects in conjuction with externally applied voltages [1], our technique takes advantage of the SEM's own beam as a charging source and makes close resolution (<0.1μm) inspection unnecessary until appropriate. In this way, defects can be located and identified using ∼/20th the time presently required.

We report on the development of an evaporated diffusion barrier for incorporation into the metallizations currently used in GaAs MMICs. Results indicated that TiN films formed by reactive ion beam assisted evaporation - the simultaneous evaporation of metal atoms and bombardment with reactive ions - were as stable as TiN films formed by reactive sputter deposition and far superior to films formed by reactive evaporation. In addition the formation of these films is compatible with photoresist lift-off techniques. Chemical and electrical analysis has shown that these films are effective barriers against Au, Ga and As diffusion under extensive (up to 1500 hrs) elevated temperature storage (280°C). TiN-Au gate electrodes whose electrical characteristics are comparable to conventional Ti-Pt-Au gates have also been fabricated.

Diffusion-reaction analysis of a two step process in which a tungsten silicide barrier layer is deposited in a rectangular trench by low pressure dichlorosilane reduction of tungsten hexafluoride followed by a complete tungsten fill by low pressure hydrogen reduction of tungsten hexafluoride reveals that high step coverage and high deposition rate can be readily achieved with logical selection of process parameters. This fact, coupled with the potential for accomplishing these deposition steps in the same single wafer reactor, suggests that this two step process may offer a high throughput alternative to blanket tungsten deposition by silane reduction.

Previously our group[1,2] has demonstrated metal-thin insulator- silicon Schottky diode structures which allow the Si Schottky barrier height to be adjusted over nearly the full range of the silicon band gap by appropriate choice of insulator thickness and metal. However, previous attempts to achieve a structure with a high barrier height to p-type that is stable above 400C(using primarily Titanium) have failed. In this paper we report on results for a metal, Molybdenum, which has a stable tie line to Sio2 and Si3N4 in metal-silicon-oxygen(nitrogen) ternary phase diagram which leads to a more stable system.

In this paper we characterize the thin film formed by rapid thermal anneal of a magnetron sputtered titanium film in a nitrogen atmosphere. The barrier properties of this material have been characterized for both n- and p-type junctions in our CMOS technology. We have characterized the physical properties of the film using Auger, RBS and TEM analysis in the same range of temperatures, and find that as the annealing temperature is increased a better quality TiNxOy film is formed. The electromigration characteristics for Aℓ/TiNxOy/TiSi2 runners, as well as the role that this system plays in minimizing failures due to stress induced voiding are examined in this study.

We have characterized the Al/RuO2 interface after annealing at temperatures in the range 450° C-550° C for durations up to several hours by backscattering spectrometry, cross-sectional transmission electron microscopy, and electrical four point probe measurement of specially designed structures. The electrical measurement yields the specific contact resistance of the interface by applying a transmission line type model developped for this purpose. An interfacial aluminum-oxygen polycrystalline compound is shown to grow with annealing temperature and duration, with a concurrent reduction of a thin layer of RuO2. However, the specific contact resistance between Al and RuO2 is found to decrease with annealing duration at 500°C. This last result indicates that the interfacial reaction does not lead to an insulating interface as could have been expected if the growth were pure and dense A12O3.

Bilayers of Cu with TiSi2 and TaSi2 were tested by furnace annealing at temperatures from 200 to 500°C. Rutherford Back Scattering (RBS) technique was used to investigate the interaction between various films and determine the stability of Cu on silicide structures. The sheet resistance was also monitored. The results show that Cu on TiSi2 and TaSi2 structures are extremely stable structures at annealing temperatures in the range of room temperature to 500 °C. In such structures, therefore, there will not be a need of any diffusion barrier between Cu and the silicide films.

We have applied angle-resolved laser scatterometry to characterize the morphology of metals deposited under various conditions. Scatterometry is a rapid, noncontact and nondestructive diagnostic which yields surface statistics including rms roughness and power spectral density of the microstructure.

This paper reports a systematic study of the properties of Al(Cu 0.5-1.5%) and Al(Cu 0.5-1.5%, Si 0.5-1.5%)alloys. The effects of deposition temperatures ranging from room temperature to 475°C were studied as well as whether the films were deposited on Ti-W or SiO2. The Cu and Si profiles were measured as well as the presence of Al2Cu and Si precipitates. The effects of post deposition bake treatments are also discussed.

Electrical properties of metal/GaAs system are known to be influenced very much by GaAs surface condition before the metal deposition. The surface condition of GaAs epitaxial layer can be affected by the wet chemical treatment of the surface. The influence of different processes were compared to choose the best technique for a high quality ohmic contact technology. Applying a chemical treatment which contains degreasing process, a light surface etching and a rinsing process, the carbon contaminations, 20-25 nm GaAs surface layer and the native oxide layer are removed from the GaAs surface. The benefit of the rinsing step is to produce a reproducible, stable surface condition before the metallization. Since the importance of the finishing step was assumed, the investigated processes differed in this step. The compared methods finished with either alkaline, like NH4OH, or acidic, like HCl, etchants resulted higher specific contact resistance than the process finished with neutral, high purity (18 MΩcm) water. In the latest case the obtained specific contact resistance was (6.4 ± 2.7) ×10−6 Ωcm2 on a GaAs epitaxial layer with the doping concentration 1.5 × 1017cm−3.