The dependence of room temperature oxidation of silicon catalyzed by Cu3Si on silicide thickness, silicide grain size and the substrate orientation has been investigated by transmission electron microscopy and x—ray diffractometry.

The extent of oxidation was found to depend critically on the thickness of starting Cu3Si film. The oxidation was found to be more restricted on (lll)Si than that of (001)Si samples. The thickness of SiO2 layer was found to decrease with the average grain size of the starting Cu3Si layer. HRTEM revealed that the oxidation is initiated at the grain boundaries. Oxide film as thick as 4.5 μm was grown at room temperature over a period of two weeks in (001) samples. The growth of thick oxide film was achieved by minimizing the grain size of Cu3Si through a reaction between Cu and an intermediate amorphous silicon layer at 200 °C.

Copper films are etched at a low temperature of 60 °C using a Cl2 plasma etching method with IR light irradiation. The etch rate is as high as 1 μm/min. The anisotropic Cu line patterns are obtained independent of the Cl2 gas flow rate and the etching pressure conditions. Moreover, there is no corrosion on the etched sample.

Availability of diffusion data is important in the evaluation of the prospect of substituting Cu for Al-Cu metallization for improving electrical and electromigration performance. Measurements have been made of 67Cu radioactive tracer diffusion in Cu, Cu-0.4Zr and several Al-Cu thin films of commonly used compositions. Grain boundary self diffusion in Cu is described by δDb= 1.5xl0-9 exp( — 0.92eV/kT) cm3/ sec. The activation energy for Cu diffusion in Al, Al-l%Cu and Al-0.5Cu-0.15Ti thin films depends on the amount of Cu present and varies in the 0.4 - 1.0 eV range. The measured diffusion parameters in the two alloy systems are compared and contrasted with those available from electromigration studies.

TiH2 has been considered as a diffusion barrier and adhesion promoter between oxide and Cu. This phase is formed by reaction of Ti with hydrogen during rapid thermal annealings. In this investigation the stability of TiH2 on PECVD and thermal oxides has been studied during Ar anneal at 400 and 500°C. X-ray diffraction, sheet resistance measurements, RBS, and nuclear reaction technique to profile hydrogen have been used in this study. The results indicate that the stability of TiH2 is dependent on the nature of the oxide, for example, the water concentration and the density of the oxide and on the temperature of the anneal. These results will be discussed in view of the applicability of TiH2 which has a low thin film electrical resistivity of about 100 μΩ-cm.

The thermal stability at the Cu / SiO2 interface has been studied as a function of the annealing atmosphere composition. Using either good vacuum conditions or refractory metal encapsulation, no copper diffusion into SiO2 has been found even for thermal treatments at 500°C for l0h. Moreover, a noticeable accumulation of the refractory metal, ( Cr, Ti ), at the Cu / SiO2 interface has been observed. The diffusion phenomena allows the self-aligned formation of a refractory metal barrier layer at the SiO2 surface.

Cu(Ti 27 at. %) and Cu(Cr 26 at. %) codeposited on silicon dioxide substrates were annealed in a flowing NH3 ambient at 400 - 600°C for 30 min. The Ti segregates to both the surface to form a TiN(O) layer and to the alloy/SiO2 interface to form a Ti-oxide/Ti-silicide bilayer. The Cr seems to migrate only to the free surface to form a CrNx layer. A 45 nm - thick Al film was deposited after nitridation, whereupon a second anneal was performed to evaluate these nitride layers as diffusion barriers. It was found that the Ti-nitride was stable up to 500°C as compared to Cr-nitride at 600°C.

Difficulty during plasma etching and post-etch corrosion are major drawbacks of Al-Si-Cu alloy films, when used for integrated circuit interconnect. Moreover, the relatively large solute mobility of Cu in Al may lead to void formation by precipitate coarsening. As integrated circuit dimensions decrease reliability issues, such as electromigration and mechanical stress voiding, are becoming increasingly important. At present several types of Al alloys are considered as possible alternatives for Al-Si-Cu: Al-Pd, Al-Sc, Al-Pd-Cu, Al-Si-Pd, Al-Si-V, Al-Si-Sc, Al-Si-Pd-Nb, and Al-Si-V-Pd. The latter quaternary alloy has been designed such as to combine the positive aspects of both Pd and V. In comparison with Cu in Al, a) the (low temperature) solid solubility is negligible for Pd and small for V, and b) the mobility is similar for Pd, but very small for V.

With transmission-electron microscopy, passivated Al-Si-Cu alloy films have been studied after thermal stressing at 200 °C: ө-Al2Cu coarsening was observed together with void condensation. Lifetests on unpassivated Al-Si-V-Pd alloys at 180 °C and 2xl06A/cm2 have shown an extremely high resistance to electromigration. Electromigration and microstructural data on these quaternary alloys will be presented. These findings suggest how the microstructure is stabilized by the combined action of the V and Pd solute atoms, a) by nm-scale (A1,V) precipitates within the Al grains and b) by small (Al,Pd) particles at the Al grain boundaries. Furthermore, the key issues in terms of reliability related microstructural phenomena are both solute and solvent mobilities in grain interiors as well as along interfaces and grain boundaries. Arguments will be given showing that at low solute concentrations the metals (V and Pd) each by themselves are not effective enough to influence the solvent motion of aluminium along interfaces and grain boundaries significantly. The combination of the two metals, however, was found to be very effective.

This paper describes in situ post deposition treatment technologies to fortify the coherent PVD TiN barrier so that it will withstand the high temperature (> 450°C) Al deposition or flow process for sub-0.5 μm planarized Al technology. The coherent PVD TiN barriers were sputtered under 3 different pressure conditions and subsequently heat treated for fortification. Such heat treated, fortified PVD TiN barriers exhibit low reactivity with Al, which is illustrated by the minimal sheet resistance increase in TiN/Al thin film stacks during the heat treatment. Furthermore, optical and SEM inspection on the silicon surface show no pitting.

Leakage current of less than 50 pA has been obtained on 10K-contact chains of sub-0.5 (μm devices using a vacuum integrated coherent Ti/fortified PVD TiN/planarized Al process. This development has led to a completely vacuum integrated sub-0.5 μm PVD Al plug fill process.

For the electromigration test of Si/TaSi2/(Al-1wt%Si) and Si/TaSi2/TiN/(Al-1wt%Si) multilayer contacts we employed the special test structures which allow to passage a pulsed electrical current through the semiconductor region lying under investigated contacts and insulated from them by n+/p-junction. The contacts were tested in the optimal conditions (temperature was cycled in the ranges from 50°C to 175°C with 300ms thermal cycle period at 25 mA constant electrical current passaged through the investigated contacts). It has been shown that the electromigration life time has been shortened by more than an order of the magnitude compared to 200°C constant temperature test. SEM investigations of the sputter deposited thin film of multilayer contact have also shown that the Al-Si thin film on the TaSi2 layer had a fine structure with the average grain size about 0,3 μm. However a presense of the TiN interlayer with the thickness of 0.05 - 0.1 pm results in an increase of the average grain size of the upper Al-Si film up to 0,8μm. The result is the increase in the electromigration process activation energy that improves the electromigration life time contacts containing the TiN interlayer.

The performance of GaAs devices is significantly influenced by the qualities of the substrates, Schottky and Ohmic contact materials. Development of Ohmic contact materials is far behind compared with that of the other materials. Low resistance, alloyed AuGeNi Ohmic contacts have been extensively used in the current manufacturing GaAs devices. However, extension of usage of these devices to Very Large Scale Integration levels requires the contacts with excellent thermal stability, shallow diffusion depth, and smooth contact surface in addition to low contact resistance. In the present paper recent studies for development of Ohmic contacts which improve the poor contact properties of the alloyed Ohmic contacts are reviewed.

This paper briefly reviews the standard Transmission Line Model (TLM) commonly used to measure the specific contact resistance ρc and the sheet resistance Rsk beneath a planar ohmic contact. In the case of an alloyed ohmic contact, a more realistic three layer (Tri-Layer Transmission Line Model (TLTLM)) can be used for the analysis. This model is based on three layers (metal layer, alloyed semiconductor layer and the unalloyed semiconductor layer) and the two interfaces between them. By using appropriate TLTLM parameters, it is possible to calculate the sheet resistance Rsk that has been experimentally derived from the standard TLM. The new TLTLM model predicts that values of Rsk greater and less than Rsh (the unmodified epitaxial layer sheet resistance) are possible in agreement with experimentally reported observations.

Ti/Pt and W/pt was used form contacts on hevily doped InAs and InGaAs emitter layers of heterojunction Bipolar transistors (HBTs) . The as deposited contacts were ohmic for Ti/Pt on InAs and W/Pt on InGaAs. The rapid thermal annealing was performed in the temperature range of 300-600 C. The contact characteristics of Ti/Pt and W/Pt were compared with Au/Cr contacts.

Very low-resistivity non-alloyed ohmic contacts (Rc) to both p- and n-GaAs were realized using molecular beam epitaxy (MBE) in a vacuum integrated system. Three different metals of Au, Ag, and Nb were in-situ deposited on (1) p+-GaAs which was heavily Be-doped either in a uniform doping or with a 5-doping scheme; and (2) n+-GaAs which was doped in a 5-pair Si δ-doping with a spacer GaAs-Si 2.5 nm thick. In both cases, low Rc values of ≤ (1-5) x 10-7 Ω-cm2 were achieved.

The structural evolution of Ni/Au/Te/Au contacts on n-GaAs (001) was examined, in correlation with their electrical properties as a function of rapid thermal annealing in the temperature range 350 - 600°C. It was found that heating at temperatures ≥ 550°C results in the formation of ohmic contacts, while contacts annealed at lower temperatures remain nonohmic. Transmission electron microscopy revealed that heating ≥ 450°C leads to extensive reactions between Ni/Au/Te/Au and GaAs and deep spike formation into the GaAs. The major reaction products were identified as NiAs and β-AuGa. Ga2Te3 grains, growing epitaxially on GaAs, were detected only in 550°C annealed samples. Heating to 600°C caused considerable Ga2Te3 loss. Implications of these results concerning the ohmic contact formation mechanism are discussed.

Ohmic contacts, with metallization scheme of Pd/Ge/Ti/Pt, were formed on heavily carbon doped GaAs and AlxGa1-xAs. The lowest specific contact resistances were 4.7x10-7 and 8.9x 10-6 Ω-cm2 for the p+-GaAs and Al0.26Ga0.74As. The p+-GaAs and Al0.26Ga0.74As were doped with carbon to 5x1019 and 2x1019 cm-3 respectively. Interfacial reactions and elemental diffusion of the contacts were investigated via transmission electron microscopy and Auger electron spectrometry with depth profiles.

Electrical, structural and reaction characteristics of In-based ohmic contacts to n-GaAs was studied. Attempts were made to form a low band gap interfacial phase of InGaAs to reduce the barrier height at the metal/semiconductor junction and thus yielding a low resistance, high reliability contacts. The contacts were fabricated by e-beam sputtering Ni, NiIn and Ge targets on VPE grown n+-GaAs film (∼1μm, 2xl018 cm-3) in UHV as the structure of Ni(200Å)/NiIn ( 100Å)/Ge(40Å)/n+-GaAs/SI-GaAs, followed by rapid thermal annealing at various temperatures (500-900 °C). The lowest specific contact resistivity (pc) of (1.5±0.5)xl0-6 Qcm2 measured by transmission line method (TLM) was obtained after annealing at 700 °C for 10s. Auger sputtering depth profile and transmission electron microscopy (TEM) were used to analysis the interfacial microstructure. By correlating the interfacial microstructure to the electronical properties, InxGa1-xAs phases with large fractional 'area grown epitaxilly on the GaAs were found to be essential for reduction of the contact resistance.

A systematic study of the enhancement of Schottky barriers to n-GaAs diodes has been carried out using the Ni-Al binary system. The diodes, Ni2Al3/n-GaAs, Ni2Al3/Ni/n-GaAs, Ni/Al/Ni/n-GaAs and NiAl/Al/Ni/n-GaAs, have been realized by sputter deposition at a base pressure ∼2xl0-7 Torr. A high Schottky barrier height ranging from 0.95 to 0.98 eV (deduced from current-voltage measurements) was observed for all the annealed contacts except for Ni2Al3/n-GaAs contacts. The enhancement of the Schottky barrier height in all the contacts was attributed to the formation of a high Al content (Al,Ga)As layer at the metal/semiconductor interface. The formation of this (Al,Ga)As layer was explained in terms of a regrowth mechanism. In this mechanism, Ni reacts with GaAs initially at low temperatures, forming NixGaAs. The NixGaAs layer is believed to react with the Ni-Al layer to form the (Al,Ga)As layer when subjected to a high temperature annealing. A (200) dark field XTEM image of the annealed contact was used to demonstrate the existence of this (Al,Ga)As phase.

Lateral variations in the Schottky barrier height (SBH) formed at Au/PtSi/(100)Si and Au/(100)GaAs diodes were measured on length scales ranging from a few to several hundred nanometers using ballistic electron emission microscopy (BEEM). All of the contacts investigated showed SBH spatial inhomogeneity. The most severe SBH variations observed were 0.09eV/0.7nm in Au/(100)GaAs contacts and 0.08eV/14nm for Au/PtSi/(100)Si contacts. Based on the lateral maps of the SBH at each interface, the difference between the locally averaged SBH and the globally averaged BEEM SBH was computed. This analysis showed that there is a critical diode length scale below which the SBH deviates significantly from the SBH averaged over a macroscopic length scale. This result implies that the uniformity of electrical characteristics of arrays of small devices (e.g.. PtSi/Si photodetectors and GaAs FET gates) can be expected to deteriorate significantly when device dimensions decrease below the critical length.

Recent reports on refractory metal nitrides/n-GaAs Schottky contacts have demonstrated that improved electrical performance can be obtained after annealing at temperature between 750 and 850°C . It is thought that a p+-type layer should be responsible for this phenomenon, which may be generated by N or N related defects. In this paper, the role of nitrogen in SI-GaAs and n-GaAs has been investigated by Hall effect and DLTS measurements. No evidence of the formation of a p+-type layer has been observed. A deep energy level of Ec-0.36eV which is thought to be related to N and an enhanced effect of N on the density of EL2 level were observed. DLTS and SIMS techniques were used to study the interface of TiN/n-GaAs Schottky contacts. The Ti3+(3d1)/Ti2+(3d2) single acceptor level at Ec-0.21 eV was observed, but the EL2 donor level is dominant. Combining the experimental results, a discussion is made about the reasons for the improvements of electrical performance after annealing.

The Ge/Pd/n-GaAs ohmic contact structure constitutes a near-ideal model system to test the applicability of the different metal/GaAs ohmic contact models. After annealing, an atomically flat interface between the GaAs substrate and a regrown Ge layer is obtained. A main point of discussion is whether the ohmic conduction across this junction either occurs by an enhanced Ge-doping of the GaAs (regrown) substrate surface layers (the doping model), and/or by a degenerate As-doping ot the Ge overlayer (the heterojunction hypothesis). In order to examine the applicability of both models, a Raman study of this system is undertaken. By a backside thinning procedure, a metallization/60 nm GaAs structure is preserved, allowing for a backside optical analysis of the regrown Ge/GaAs interface region.