We have investigated the structure of sputter deposited amorphous and crystalline indium oxide films by electron diffraction. Selected area diffraction patterns were recorded for both states from which radial density functions were derived. The comparison of the crystalline radial density function to the amorphous one shows that the first nearest neighbor distance corresponding to the In-O bond length is 2.2Å and is the same for both states. A model density function for crystalline structure was used to explore the difference in higher order peak positions. We report that the In-In separation in amorphous state has a single characteristic distance of 3.6Å compared to the crystalline state which has two non-equivalent In sites and consequently different separations as In(1)-In(2) at 3.4Å and In(2)-In(2) at 4.3Å.

MFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.

Surface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

We have developed a novel growth method for single-crystalline film of natural superlattice oxides and named the method “Reactive Solid-Phase Epitaxy (R-SPE).” Single-crystalline thin films of homologous series In-GaO3(ZnO)m (m=integer) are fabricated by the R-SPE method and its growth mechanism, especially a role of ZnO epitaxial layer, is clarified. High-temperature annealing of bi-layer films consisting of an amorphous InGaO3(ZnO)5 layer deposited at room temperature and an epitaxial ZnO layer on YSZ substrate allows for the growth of single-crystalline film with a controlled chemical composition. The ZnO layer plays an essential role in determining the crystallographic orientation, while the thickness ratio between the two layers controls the film composition.

Y2O3 thin films were grown directly on Si (001) by MBE and annealed in-situ under UHV at various annealing temperatures. The samples were investigated in-situ by RHEED and ex-situ by HRTEM. A 7 to 15 Å thick non-uniform interfacial amorphous layer is observed in the as-grown sample. After annealing at 490°C under UHV for 30 minutes the amorphous layer is reduced and a sharp Y2O3/Si interface is obtained. At higher annealing temperatures, YSi2 islands start to form at the Y2O3/Si interface. I-V measurements performed on generic MIS structures show that the annealed samples exhibit higher leakage current density than the as-grown sample, due to reduction of the wide band gap interfacial layer. Leakage current densities in annealed samples remain below 1A/cm2, which is acceptable for future high-κ transistor fabrication.

Growth of epitaxial Si epitaxial overlayers on lattice matched (LaxY1-x)2O3/Si (LaYO/Si) structures has been investigated by high resolution transmission electron microscopy and reflection high energy electron diffraction. Results indicate that smooth two-dimensional near lattice-matched LaYO (111) films can be grown on Si (111) substrates. However, subsequent Si epitaxial growth on the LaYO/Si structures nucleates as three-dimensional islands, a consequence of the high energy of the Si overlayer/LaYO interface. We have investigated the effect of growth temperature on the microstructure of the Si overlayers. Higher temperatures resulted in the nucleation of large faceted islands and rough overlayers while lower temperatures result in smaller islands that coalesce at an early stage and produce smoother films. In addition, formation of planar defects in these films is attributed to stacking errors on the {111} facets of initial Si islands with lower temperatures resulting in a higher density of stacking faults and twins.

For staked structures consisting of evaporated ZrO2 and ∼0.6nm-thick silicon oxynitride formed on Si(100), the blocking capability of the silicon oxynitride against oxidation in dry-O2 anneal at 500°C has been studied as a function of nitrogen content in the barrier layer in the range within ∼11at.%. With increasing nitrogen content, the interfacial oxide thickness is decreased linearly and, to suppress the growth of the interfacial oxide layer within two monolayers, a nitrogen content of ∼10at.% is necessary. Observed efficient blocking against oxidation, even for the case with a nitrogen content as small as ∼6at.%, is attributable to the improved homogeneity in the Si-O-Si bonding features at the interface by nitrogen incorporation of a few at.%, which is suggested from the experimental fact that the bandwidth of LO phonons near the interface due to the nitrogen incorporation is decreased as obtained by FT-IR-ATR measurements.

In present report, we have studied the initial stage of the growth of crystalline yttria-stabilized zirconia (YSZ) films on the natively oxidized Si (100) wafer by pulsed-laser deposition. X-ray photoelectron spectroscopy (XPS) and high-resoluti on transmission electron microscopy (HRTEM) show that, for the first few monolayers of crystalline YSZ deposited on Si (100), the dynamic processes appear to be the decomposition of SiO2 to SiO, the formation of ZrO2, and the desorption of SiO. The native amorphous silicon oxide layer is removed completely with the continued deposition of YSZ and the oxygen in this layer is used as oxygen source for forming stable crystalline oxide film. XPS depth profile and HRTEM investigation showed that the interface of crystalline YSZ film in contact with silicon was found to be atomically sharp and commensurately crystallized without an amorphous layer. The interface structure is suggested to have a sequence of-Si-O-Zr-O-. For the film with electrical equivalent oxide thickness 1.46 nm, the leakage current is about 1.1×10- A/cm2 at 1 V bias voltage. The hysteresis and interface state density in this film are measured to be less than 10 mV and 2.0×1011eV-1cm-2.