Copper is most widely used interconnect material in present silicon microelectronic technologies. As such, multiple interfaces formed by a thin Cu layer and other materials must be engineered to achieve the desired chemical, mechanical, and electrical properties. Adhesion between Cu and the barrier layer, as well as between Cu and the dielectric, is of particular interest, due to its role in controlling interfacial stability and Cu electromigration behavior [1]. This work focuses on understanding how the interface chemistry affects adhesion. Firstprinciples density functional theory (DFT) calculations were used to determine chemical adhesion energies of interfaces formed by Cu and various metals considered as a diffusion barrier, including Ta, TiN, and W. Calculations predicted increasing adhesion strength in the order of TiN < Si-doped TiN < TaN < Ta, consistent with wetting experiments done using 100Å thick Cu layer samples. The effects of doping at the interface using light elements (C, N, O) were also determined. Calculations were also done for interfaces of Cu with two different classes of amorphous dielectric materials, i.e. silicon nitride and silicon carbide, for which detailed material characterizations are often difficult and time consuming. Calculations predicted Cu/Si-nitride and Cu/Si-carbide adhesion strengths consistent with 4-pt-bend experiments, including the improvement in adhesion energies when silicon was used to dope the interface. In addition, weaker interfaces provide low-resistance diffusion paths for Cu atoms during electromigration. The first-principles based modeling, validated by select adhesion measurements, provides a predictive approach to effectively determine adhesion strengths and predict electromigration reliability in interconnects.

Post ash chemical treatments were evaluated for improving the reliability of Cu/low-k structures. The RC delays, leakage current, ramp-voltage-breakdown and timedependent- dielectric-breakdown lifetimes resulting from different treatments were compared. The pitch dependence of capacitance and breakdown was also evaluated. Post ash chemical treatments were more beneficial for the smaller line spaces. FTIR and TEM/EELS analysis were performed to determine the chemical changes occurring at the sidewall due to the post ash chemical treatments. The analysis showed that the chemical treatments increased the carbon content at the trench sidewalls. The post ash treatments were found to improve the electrical characteristics.

White Sn (β-Sn) thin film stripe shows a voltage drop about 10% when subjected to electromigration testing. Since β-Sn has anisotropic crystal structure, it possesses different resistivity along a-, b- and c axis. The direction of the axes determines the resistance in each grain. Under electromigration, low resistance grain tends to grow in the expense of the neighboring high resistance grains. The changes of grain orientation in the Sn stripe before and after electromigration was studied by synchrotron x-ray microdiffraction (∼1νm diameter) to achieve grain-by-grain analysis. Grain growth involves grain boundary migration and rotation of neighboring high resistance grains. A model different from normal grain growth is proposed to describe the condition and mechanism of microstructural evolution under electromigration.

Experiments on three-terminal ‘dotted-I’ test structures (copper metal lines with vias at both ends and an additional via at the center) show that the mortality of a single segment not only depends on the values of its current density and length, but also on the stress conditions in the linked segment. The current density in one 25μm long segment was fixed at 0.5MA/cm2, with electron flow toward the central via. In the othersegment, the current magnitude and sign were varied for different test populations, with the current varied from 2.5MA/cm2 to -2.5MA/cm2 with intermediate values including zero. For all cases, some test structures survived for the full 780 hours of testing and some did not. The percent of the lines that failed increased monotonically with an effective jL product defined as the maximum of the sum of the jL products from all paths through the structure. However, some lines with smaller than expected effective jL products failed, and some lines with relatively large effective jL products did not. Simulations of electromigration and electromigration-induced failures for all test conditions have been carried out. We find that test conditions leading to extreme values of the effective jL product probe different failure mechanisms than those associated with intermediate effective jL products. It is also shown that the definition of the effective jL product must be modified to account for zero current (inactive) segments that act as reservoirs or sinks. Multi-via test structures in general, and dotted-I test structures specifically, are shown to be versatile tools for identification and characterization of different failure mechanisms and length effects through the use of different test conditions with a single fixed structure.

Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

The line width dependence of stress in damascene Cu was examined experimentally as well as with a numerical simulation. The measured hydrostatic stress was found to increase with increasing line width. The larger stress in an interconnect with large dimension is attributed to the larger grain size, which induce higher growth stress in addition to thermomechanical stress. A stress model based on microstructure was constructed and the contribution of the growth and thermal stress of the damascene lines were quantified using finite element analysis. It was found that the stress of the via is lower than that of wide lines when both the growth stress and thermal stress were considered. This stress gradient between via and line, which is the driving force of vacancy diffusion, is larger when the low-k with lower stiffness and higher thermal expansion is used for dielectric layer. For this reason, the Cu/low-k can be more vulnerable to stress-induced voiding.

At present, Pb-free process is imperative in the electronic packaging industry. Many reports focus on Pb-free solder to improve the solderability, it seems not obtain wettability as good as SnPb solder. In this study, an alloy interlayer with different content was deposited on Cu to balance wettability and diffusion barrier in the interface of joint by electroplating process. There are three types of interlayers including Cu, Ni, and SnNi alloy. The interlayer may react with Sn-3.5Ag solder during reflow process. Sn-Ni alloy plating layer is selected to improve wettability and provide diffusion barrier at the same time in soldering process. For interfacial microstructure examination, morphology characterization can be obtained by using scanning electron microscope (SEM) and energy-dispersive x-ray analysis (EDX). The structure of IMC is identified by x-ray diffraction (XRD).

A new organic precursor was designed and synthesized in order to form polymer films having low dielectric constants by a plasma-enhanced co-polymerization (PCP) technology. The organic monomer features a large aliphatic hydrocarbon structure, tricyclodecane (TCD) group. Optimized polymer films deposited from the monomer had dielectric constants less than 2.5. A solid 13C-NMR spectrum showed that the TCD moiety in the precursor was included in the polymer without changing the structure. The effect of the deposition temperature on the film structure was studied by analyzing Raman spectra. It was revealed that the dielectric constant is strongly associated with sp2 carbon content in the TCD-based polymer films.

Three-dimensional (3D) wafer-level integration is receiving increased attention with various wafer bonding approaches being evaluated. Recently, we explored an alternative lowtemperature Ti/Si-based wafer bonding, in which an oxidized silicon wafer was successfully bonded with a prime silicon wafer at 400°C using 30 nm sputtered Ti as adhesive. The bonded pairs show excellent bonding uniformity and mechanical integrity. Rutherford backscattering spectrometry (RBS) was applied to confirm the interdiffusion occurred in the interlayer. The bonding interface was examined by high-resolution transmission electron microscopy (HRTEM) assisted with electron energy loss spectroscopy (EELS) elemental mapping and energy dispersive X-ray spectroscopy (EDX). Characterization of the bonding interface indicates the strong adhesion achieved is attributed to an amorphous layer formed by interdiffusion of Si and oxygen into Ti interlayer and the unique ability to reduce native oxide (SiO2) by Ti even at low temperatures.

Electromigration in solder joints causes a void formation between intermetallic compounds (IMC) and solder at the cathode. The effect of electromigration in mechanical test of Cu wires joined by solder was performed. The current density of electromigration was 1∼5×103 A/cm2. The working temperature was 100∼150°C. Tensile stress and shear stress were applied either before or after electromigration. The tensile strain rate was 3 μm/min. We observed that, without electromigration, tensile stress caused a ductile break at the middle of solders because the solder was softer. On the other hand, if combined with electromigration, a brittle failure always occurred at the cathodes interface during tensile test. The ultimate tensile strength decreased with longer electromigration time or higher current density. In shear test, the daisy chain of solders failed alternatively at the cathodes after electromigration.

Ultra-thin ALD-TaN/PVD-Ta liners have been developed to prevent Cu diffusion into porous interlayer dielectric (ILD) materials envisioned for future copper interconnections. The porous ultra-low k (p-ULK) film is prepared using the spin-on method, and typical k-value and the average pore size of p-ULK used in this paper are 2.3 and 2-3 nm, respectively. Interaction and phenomena at the ILD/ALD-TaN interface have been investigated, and the electrical measurements of samples with a bi-layered ALD-TaN/PVD-Ta barrier were performed after completing the metallization and CMP process.

A deep penetration of ALD-TaN was observed on the as-deposited p-ULK, which is due to the interconnected pore structures. However, the surface of the p-ULK is drastically changed after the etch process, where changes are attributed to plasma damage and re-deposition of etched species. Pores can therefore be sealed during the etch process. Furthermore, the plasma damage makes the sidewall more hydrophilic, which may promote the growth of ALD-TaN layer. Based on EELS and EDS profiles, there is no signature of TaN penetration into the etched p-ULK at M1 level with a sharp Ta peak, which indicates excellent stability of ultra-thin ALD-TaN liner.

An oxidation test in air ambient and at elevated temperature confirmed the barrier properties of the stacked ALD-TaN/PVD-Ta layers. Any weak point in the barrier allows the Cu to oxidize and to make a color change under an optical microscope. However, all of our samples showed no color change, which implies that the barrier is very uniform and stable. Electrical properties measured at M1 showed excellent results. Our results demonstrate the ability to successfully integrate ALD-TaN barriers with a nanoporous ULK film.

A spherical nanoindentation method was developed to evaluate elastic and plastic deformation parameters. The experimental reliability was confirmed by examining fused silica in the elastic deformation range. Yield stress as a quantitative plastic parameter was estimated using the Hertz contact theory and Tresca yield criterion. A copper thin film and two types of low-k thin film were examined. Reduced modulus was almost the same as the value obtained for the Cu (100) plane and yield stress was found to be between single crystals Cu (111) and Cu (100). These mechanical properties were thought to be dependent on the crystal orientation of the copper thin film. The two types of MSQ low-k film exhibited a difference in yield stress, although hardness was estimated to be similar by using the conventional nanoindentation method. These results have never been seen on a micro-mater scale.

In this study the stress evolution for the entire transistor fabrication process is simulated and the packaging stress is modeled as the external pressure/normal stress acting on the boundaries of the transistor unit cell. The impact on device performance from both the fabrication stress and the packaging stress is investigated using a classical piezo-resistance mobility model. The effect of the packaging stress on device mobility can be either beneficial or detrimental depending on whether the stress is tensile or compressive, on stress pattern, its magnitude, and the transistor type. The results suggest that utilizing both the fabrication stress and the packaging stress for stress engineering can lead to additional device performance enhancements.

Low-κ dielectrics have to meet stringent requirements in material properties in order to be successfully integrated. A particularly difficult challenge for material development is to obtain a combination of low dielectric constant with good thermal and mechanical properties. Incorporation of low dielectric constant materials such as porous silica based materials as a replacement to conventional dielectrics like SiO2 and use of Cu metallization schemes has become a necessity as critical dimensions of devices decrease. This paper is focused on the challenges in developing materials with low dielectric constant but strong thermo mechanical properties. Thin films of Ultra-Low materials such as porous Methyl Silsesquioxane (MSQ) (κ=2.2) were implanted with argon 1 × 1016 cm-2 dose at energies varying from 20 to 50 keV at room temperature. This work shows that the surface hardness of the porous films can be improved five times as compared to the as-deposited porous films by implanting Ar with 1 × 1016 cm-2 doses at 20 keV, sacrificing only a slight increase (∼9%) in dielectric constant (e.g., from 2.2 to 2.4). The hardness persists after 4500C annealing. In this current work, an ion implantation strategy was pursued to create a SiO2-like surface on MSQ. The effects of implantation parameters on the barrier property and bulk stability of MSQ were then studied. The results reveal one possible route to attain the “zero barrier thickness” requirement for interconnects systems.

Reliability of today's interconnect lines in microelectronic devices is critical to product lifetime. The metal interconnects are carriers of large current densities and mechanical stresses, which can cause void formation or metal extrusion into the passivation leading to failure. The modeling and simulation of stress evolution caused by electromigration in interconnect lines and vias can provide a means for predicting the time to failure of the device. A tool was developed using MathCAD for simulation of electromigration-induced stress in VLSI interconnect structures using a model of electromigration induced stress. This model solves the equations governing atomic diffusion and stress evolution in one dimension. A numerical solution scheme has been implemented to calculate the atomic fluxes and the evolution of mechanical stress in interconnects. The effects of line geometries and overhangs, material properties and electromigration stress conditions have been included in the simulation. The tool has been used to simulate electromigration-induced stress in pure Cu interconnects and a comparison of line stress predictions with measured electromigration failure times is studied. Two basic limiting cases were studied to place some bounds on the results. For a lower bound estimate of the stress it was assumed that the interface can be treated like a grain boundary in Cu. For an upper bound estimate it was assumed that the interface can be treated like a free surface of Cu. Existing data from experimental samples with known structure geometries and electromigration failure times were used to compare the electromigration failure times with predicted stress build-up in the interconnect lines.

For 90 nm node devices, the group of materials known as organosilicate glass (OSG) has emerged as the predominant choice for intermetal dielectrics. A potential failure mechanism for this class of low-k dielectric films during the manufacturing process is catastrophic fracture due to channel cracking. The use of an electron beam curing process is being investigated for improvement in the mechanical strength of these silicon-based materials. Within this work, the effects of curing dose (micro-C/cm2) upon the mechanical properties of OSG thin films were characterized. For a set process voltage and current, linear relationships exist between the dose and several mechanical film properties. Channel crack growth velocities were also measured for these cured materials. As the cure dose is increased, the crack growth rate decreases according to a power law relationship. The structural film changes induced by the electron beam cure process are addressed, focusing on their impact upon the mechanical strength of OSG thin films.

Continuing miniaturization of microelectronic devices requires development of low dielectric constant materials to lower the RC delay, power dissipation and crosstalk noise. Although spin-on polymer dielectrics usually have better potential for extendibility to lower dielectric constant (k) values compared to chemical-vapor-deposited dielectrics, their low mechanical properties prevent them from being successfully integrated with copper metal lines.

Recent evaluation of a new thermosetting oligomer shows high thermal stability, low moisture pick-up and low dielectric constant. Techniques to optimize the solubility and spin coating characteristics of the oligomer have been developed. The thermally cured polymer displayed a thermal stability up to 480°C in nitrogen and 400°C in air. The cured polymer displayed a dielectric constant of 2.7 at 1 MHz and a breakdown strength larger than 230 V/μm. Nanoindentation testing showed that it had an extraordinarily high Young's modulus of 16.8 GPa and a hardness of 3.5 GPa. By use of porogens, a dielectric constant as low as 1.85 was obtained while still maintaining an acceptable high Young's modulus of 7.7 GPa and hardness of 2.0 GPa. Nanoscratch testing indicated that this material had good adhesion to the Si substrate, and Ta which is a diffusion barrier for copper. These results appear unique compared to all commercially available low-k candidates.

Thin SiN films deposited by plasma enhanced chemical vapor deposition (PECVD) have been analyzed by a variety of analytical techniques including Fourier Transform Infrared Spectroscopy (FTIR), X-ray reflectivity (XRR), and Rutherford Backscattering Spectrometry/Hydrogen Forward Scattering (RBS/HFS) to collect data on bonding, density and chemical composition respectively. Both tensile and compressive SiN films have been deposited and analyzed. Mechanisms of stress formation in SiN thin films are discussed. It has been found that amount of bonded hydrogen as detected by FTIR is higher for compressive films compared to tensile SiN films. Amount of bonded hydrogen in a film is correlated well with tensile stress. Effect of deposition temperature and other process parameters on stress have been studied. Exposure of SiN films to elevated temperature after deposition lead to increase in tension and degradation in compressive stress. New approaches to stress generation in thin films like creation of multilayer film structures have been delineated.

Future microprocessor technologies will require interlayer dielectric (ILD) materials with a dielectric constant (κ-value) less than 2.5. Organosilicate glass (OSG) materials must be nanoporous to meet this demand. However, the introduction of nanopores creates many integration challenges. These challenges include 1) integrating nanoporous films with low mechanical strength into conventional process flows, 2) managing etch profiles, 3) processinduced damage to the nanoporous ILD, and 4) controlling the metal/nanoporous ILD interface. This paper reviews research to maximize mechanical strength by engineering optimal pore structures, controlling trench bottom roughness induced by etching and understanding its relationship to pore size, repairing plasma damage using silylation chemistry, and sealing a nanoporous surface for barrier metal (liner) deposition.

Templating is one of the most popular methods for generating nanocomposite and nanoporous films and the resultant pore size and pore interconnection length depend strongly on porogen concentration/porosity among other factors. Positronium Annihilation Lifetime Spectroscopy (PALS) analysis has been performed on a series of films produced using increasing concentrations of a type of cyclodextrin (CD) porogen in a modified silsesquioxane host matrix. PALS reveals the relationship between the resulting pore structure (both size and interconnection length) and porosity, which can be used to deduce pore shape. At low porogen concentration, isolated pores are resolved, but the pore size is consistent with a cluster of two or three CD molecules, rather than an individual one. As the porosity increases, the aggregation of the porogen domains appears to be more 3-dimensional (pseudo-random) with gradual increase in pore size. Computer simulations using a random pore growth model show consistent trends for pore size growth, but the agreement is poor for interconnection length. It is a key demonstration of the usefulness of PALS in untangling the fundamental pore structure and its evolution in porosity. PALS characterization of porosity provides novel feedback in the understanding and design of nanoporous materials.