In this work, we study cubic SiC/Si (111) templates as an alternative for growing GaN on silicon. We first developed the epitaxial growth of 3C-SiC films on 50mm Si(111) substrates using chemical vapor deposition. Then, AlGaN/GaN high electron mobility transistors were grown by molecular beam epitaxy on these templates. Both the structural quality and the behavior of transistors realized on these structures show the feasibility of this approach.

An AlGaAs/InGaAs HEMT grown on Si substrate with Ge/GexSi1−x buffer is demonstrated. The Ge/GexSi1−x metamorphic buffer layer used in this structure was only 1.0 μgm thick. The electron mobility in the In0.18Ga0.82 As channel of the HEMT sample was 3,550 cm2/Vs. After fabrication, the HEMT device demonstrated a saturation current of 150 mA/mm and a maximum transconductance of 155 mS/mm. The well behaved characteristics of the HEMT device on the Si substrate are believed to be due to the very thin buffer layer achieved and the lack of the antiphase boundaries (APBs) formation and Ge diffusion into the GaAs layers.

Semiconducting nanowires are emerging as a route to combine heavily mismatched materials. The high level of control on wire dimensions and chemical composition makes them promising materials to be integrated in future silicon technologies as well as to be the active element in optoelectronic devices.

In this article, we review the recent progress in epitaxial growth of nanowires on non-corresponding substrates. We highlight the advantage of using small dimensions to facilitate accommodation of the lattice strain at the surface of the structures. More specifically, we will focus on the growth of III–V nanowires on group IV substrates. This approach enables the integration of high-performance III–V semiconductors monolithically into mature silicon technology, since fundamental issues of III–V integration on Si such as lattice and thermal expansion mismatch can be overcome. Moreover, as there will only be one nucleation site per crystallite, the system will not suffer from antiphase boundaries.

Issues that affect the electronic properties of the heterojunction, such as the crystallographic quality and diffusion of elements across the heterointerface will be discussed. Finally, we address potential applications of vertical III–V nanowires grown on silicon.

III-nitride materials have different crystal structures and properties than the substrates commonly used for their deposition, including silicon, silicon carbide and sapphire. These differences, such as thermal expansion coefficient and lattice constant, necessitate the use of a transition layer to accommodate the resulting stress between substrate and the epitaxially grown III-N layers. AlxGa1−xN based transition layers are one proven solution used for the growth of device quality GaN layers on Si (111) substrates. The use of such transition layers enables the deposition of state of the art AlGaN/GaN high electron mobility transistor epitaxial structures that, upon fabrication into devices, exhibit high performance and excellent reliability.

Examination of the microstructure of these AlxGa1−xN transition layers, by transmission electron microscopy (TEM) and other methods, reveals some interesting properties that can help explain how high quality III-N epitaxy can be performed in a system with significant thermal and lattice mismatch. Observations that will be reported on and discussed in this presentation are (1) the role that a thin strain absorbing amorphous SiNx layer at the Si substrate/transition layer interface plays in the reduction of the formation of misfit dislocations, (2) the low screw dislocation density (less than ȼ107/cm2) in these III-N films relative to edge and mixed dislocation densities, and (3) the role that the substrate type and quality can play on dislocation type and density.

We report the growth and characterization of thin germanium-carbon layers grown directly on Si (111) by ultra high-vacuum chemical vapor deposition. The thickness of the films studied is 8-20 nm. The incorporation of small amount (less than 0.5%) of carbon facilitates 2D growth of high quality Ge crystals grown directly on Si (111) without the need of a buffer layer. The Ge1−xCx layers were grown in ultra high vacuum chemical vapor deposition chamber, at a typical pressure of 50 mTorr and at a growth temperature of 440 °C. CH3GeH3 and GeH4 gases were used as the precursors for the epitaxial growth. The Ge1−xCx films were characterized by atomic force microscopy (AFM), secondary ion mass spectroscopy, x-ray diffraction, cross-sectional transmission electron microscopy and Raman spectroscopy. The AFM rms roughness of Ge1−xCx grown directly on Si (111) is only 0.34 nm, which is by far the lowest rms roughness of Ge films grown directly on Si (111). The dependence of growth rate and rms roughness of the films on temperature, C incorporation and deposition pressure was studied. In Ge, (111) surface orientation has the highest electron mobility; however, compressive strain in Ge degrades electron mobility. The technique of C incorporation leads to a low defect density Ge layer on Si (111), well above the critical thickness. Hence high quality crystalline layer of Ge directly on Si (111) can be achieved without compressive strain. The fabricated MOS capacitors exhibit well-behaved electrical characteristics. Thus demonstrate the feasibility of Ge1−xCx layers on Si (111) for future high-carrier-mobility MOS devices that take advantage of high electron mobility in Ge (111).

The prospect of developing electronic and optoelectronic devices, including solar cells, that utilize the wide range of energy gaps of InGaN has led to a considerable research interest in the electronic and optical properties of InN and In-rich nitride alloys. Recently, significant progress has been achieved in the growth and doping of InGaN over the entire composition range. In this paper we present structural, optical, and electrical characterization results from InGaN films grown on Si (111) wafers. The films were grown over a large composition range by both molecular beam epitaxy (MBE) and the newly developed “energetic neutral atomic-beam lithography & epitaxy” (ENABLE) techniques. ENABLE utilizes a collimated beam of ∼2 eV nitrogen atoms as the active species which are reacted with thermally evaporated Ga and In metals. The technique provides a larger N atom flux compared to MBE and reduces the need for high substrate temperatures, making isothermal growth over the entire InGaN alloy composition range possible. Electrical characteristics of the junctions between n- and p-type InGaN films and n- and p-type Si substrates were measured and compared with theoretical predictions based on the band edge alignment between those two materials. The predicted existence of a low resistance tunnel junction between p-type Si and n-type InGaN was experimentally confirmed.

AlGaN /GaN HEMT structures were used for liquid and gas sensors. The sensitivity of pH sensors was determined after clean-in-place tests. A multigas measurement at 330°C is presented. A piezo-driven mechanical actor is demonstrated and used as a variable capacitor. GaN on silicon logic circuitry is demonstrated at 250°C.

Highly spatially resolved cathodoluminescence (HRCL) imaging and electron backscattering pattern (EBSP) study of InGaN microcrystals were achieved. InGaN grown by the nitridation of a mixture of GaN microcrystals and indium sulfide powders with ammonia at 1000°C had crystal habit with twelve prismatic planes. The prismatic planes were grouped into two groups: the first group is pentagonal shaped planes yielding blue CL (420nm) and rectangular planes without luminescence. EBSP showed that the pentagonal shaped planes are indexed to the {11-20} a-plane and the rectangular plane to the {1-100} m-plane. HRCL imaging showed InGaN accumulated at the V pits on the basal plane. The obevation indicated that the crystal qualty of InGaN and the indium contents incorpated were controlled by the indices of GaN growth planes on which InGaN grew.

Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

It is now apparent that future generations of fast electronics and compact sensors may need to rely increasingly on integrated optical components. But integration of electronics and photonics in today's IC's is challenging. Silicon, the ubiquitous electronic material, is neither ideally suited for most photonic functions nor readily integrated with most of the common photonic materials, such as GaAs. The approach we describe here relies on GaN-based films, which can be grown directly on silicon substrates and hence can be potentially integrated with state-of-the-art Si-based electronics. We have demonstrated the fabrication of GaN structures on silicon wafers ranging in overall size from sub-micron to several millimeters, all containing highly accurate individual features on the nm scale. As proof of concept, we have fabricated GaN optical waveguides and photonic crystals containing optical cavities by patterning GaN membranes grown directly on Si wafers. Our optical cavities were designed to have resonant modes within the spectral region of the broad defect-induced luminescence of GaN. We have measured sharp resonant features associated with these cavities by optically pumping above the GaN band edge, and have compared the data to numerical simulations of the spectra. Our results to date demonstrate the feasibility of fabricating high-quality GaN photonic structures directly on Si wafers, thereby providing a possible path to achieving true integration of electronics and photonics in future generations of IC's.

The replacement of native oxides with deposited oxides in CMOS technology opens the door to replacing the Si with semiconductors without high-quality native oxides. For example, the use of InSb in logic applications could allow much lower operating voltages and power dissipation due to the InSb channels reaching saturation at significantly lower electric fields. Epitaxy of InSb onto Si could be done directly or using an intermediate layer such as GaP, GaAs, or InP. In the current work we describe the growth of InSb on Si (001) and discuss the structural and electrical properties of the resulting InSb films. The samples were characterized in terms of background electron concentration, mobility, deep level traps, Hall sensitivity, and x-ray rocking curve width.

Samples were grown using molecular-beam epitaxy in a Riber-Compact 21T system. Antimony was supplied with a Veeco valved cracker cell. Vicinal Si(001) substrates offcut by 4º toward [110] were prepared by repeated oxidation and oxide-removal and then loaded into the MBE system. After the substrate temperature had been increased to about 820ºC, the surface shows a clear 24 reconstruction and appears to be free of oxide. This reconstruction remains until the substrate temperature reaches 1015ºC, at which temperature a 21 appears, indicating a dominance of double-height steps. After allowing the substrate to cool to the intended growth temperature for InSb, it is exposed to cracked Sb, resulting in the surface going from 21 to 11. This 11 reconstruction remains throughout the subsequent InSb deposition. InSb was deposited with a Sb/In flux ratio of about 5 and a growth rate of 0.2 nm/s. We have investigated growth temperatures between 300 and 420ºC for growth. To prevent the formation of the defects we introduced in some samples GaSb/AlSb supperlattice buffer layer. The best structural quality has been achieved at a growth temperature of 420ºC using GaSb/AlSb supperlattice buffer layer, resulting in our best electron mobility of 2.6104 cm2/Vs for a 2m film at room temperature. The samples grown at 420°C have the narrowest x-ray rocking curve width (FWHM of about 950 arcsec). Deep level noise spectra indicate the existence of the deep levels. The sample with the best crystal quality and highest mobility has the lowest traps. The deep levels have a temperature dependent behavior.

We report on deposition and properties of m-plane GaN/InGaN/AlInN structures on LiAlO2 substrates grown by metal organic vapor phase epitaxy (MOVPE). At first, two different buffer structures, one of them including an m-plane AlInN interlayer, were investigated concerning their suitability for the subsequent coalesced single-phase m-plane GaN growth. A series of quantum well structures with different well thickness based on one of these buffers showed absence of polarization-induced electric fields verified by room temperature photoluminescence (RT PL) measurements at different excitation intensities. Furthermore, polarization-resolved PL measurements revealed a high degree of polarization (DoP) of the emitted light with an intensity ratio of 8:1 between light polarized perpendicular and parallel to the c-axis.

The spontaneous growth of GaN nanopillars on (111) Si by plasma assisted molecular beam epitaxy has been investigated. The growth of GaN nanopillars on Si is driven by the lattice mismatch strain energy on Si and the high surface energy of the nitrogen stabilized (0001) GaN surface. A higher growth rate of nanopillars compared to a compact GaN film suggests the diffusion of Ga atoms from the uncovered substrate areas to the nucleated GaN nanopillars. The GaN nanopillars were characterized by field-emission scanning electron microscopy (FE-SEM), photoluminescence, and micro Raman spectroscopy. SEM image revealed that average diameter of GaN nanopillars was in the range of 70-100nm and an average height of 600nm. The photoluminescence (PL) spectra indicate the good emission property of the nanopillars. The low temperate PL spectrum exhibited an emission peak at 3.428eV besides a sharp excitonic peak. PL and Raman spectra indicate that GaN nanopillars are fully relaxed from lattice and thermal strain.

In this work metalorganic chemical vapor phase epitaxy (MOVPE) growth and characterization of AlInN in the whole compositional range and the impact on the development of field effects transistors (FET) structures will be presented. Due to the large difference in the lattice parameters of the binaries AlN and InN the growth of AlInN with high indium concentrations is ambitious, and first the growth conditions for the alloy will be discussed. An experimental phase diagram and corresponding theoretical calculations will be displayed. The critical layer thickness of AlInN on GaN has been experimentally determined. Relaxation of the AlInN-layer has a strong influence on the sample morphology. At indium concentration exceeding 30% an polarization induced hole gas is expected at the AlInN/GaN interface from theoretical calculations, but no p-channel conductivity could be confirmed. The absence of the two dimensional hole gas will be discussed.

In this work, we present a study of epitaxial Aluminium Nitride (AlN) for thin film bulk acoustic wave (BAW) applications. Molecular beam epitaxy (MBE) was used to perform high crystalline quality AlN thin films growth on different silicon substrate preparations. A morphological study was performed by atomic force microscopy (AFM) and scanning electron microscopy (SEM), while structural properties and acoustic wave speed were respectively assessed by X-ray diffraction and acoustic picoseconds.

The condensation method to grow a strained SiGe layer-on-insulator (ε-SGOI) has attracted interests for the application of high speed complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) because of high quality properties and effective process cost. Although many reports presented its superiority in a device performance to bonding and dislocation sink technologies, the mechanism by which the condensation method produces ε-SGOI has also not been clearly explained and the surface properties have not been evaluated. Thus, we investigated condensation mechanism in detail by characterizing a surface property and Ge profile in SiGe layer. For the experiment, first, a SiGe layer on silicon-on-insulator layer was epitaxally grown at 550 °C, and three different oxidation thicknesses were grown at 950 °C, i.e., 40, 60, 90 nm. From our investigation results, we found that there are three steps in producing ε-SGOI. For the first step, by the 40-nm-thick oxidation, a diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was generated and Ge atoms were segregated into only surface oxide. It was observed that Ge profile of SiGe layer was shown a less graded profile. And, in the second step with 60-nm-thick oxidation, Ge atoms in SiGe layer into Si layer-on-insulator was diffused further than a first step did and Ge atoms were segregated into surface oxide. It was observed that Si layer was shown a fully graded profile. Lastly, in the third step with 90-nm-thick oxidation, the diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was finished completely and Ge atoms were segregated into both surface and buried oxides. It was confirm that Ge profile of SiGe layer was shown a Gaussian profile rather than a graded profile, and dislocation sink occurred. Therefore, our talk will focus on the explanation for the mechanism by which condensation method produces ε-SGOI via characterizing a surface property, SiGe thickness, a remained Si thickness on insulator, and Ge concentration in SiGe layer.

Engineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.

The Smart Cutä technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates?

In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates.

[1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003)

[2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995)

[3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998)

[4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)

[5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)

[6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127

[7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004).

[8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118

[9] H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004)

[10] G. Meneghesso et al , IEDM 2007, to be published

[11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004)

[12] J. Dorsaz and al., Proceedings, ICNS6 (2005)

[13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005.

[14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

The electron channeling contrast imaging (ECCI) technique was utilized to investigate atomic step morphologies and dislocation densities in 3C-SiC films grown by chemical vapor deposition (CVD) on Si (001) substrates. ECCI in this study was performed inside a commercial scanning electron microscope using an electron backscatter diffraction (EBSD) system equipped with forescatter diode detectors. This approach allowed simultaneous imaging of atomic steps, verified by atomic force microscopy, and dislocations at the film surface. EBSD analysis verified the orientation and monocrystalline quality of the 3C-SiC films. Dislocation densities in 3C-SiC films were measured locally using ECCI, with qualitative verification by x-ray diffraction. Differences in the dislocation density across a 50 mm diameter 3C-SiC film could be attributed to subtle variations during the carbonization process across the substrate surface.

In the last decade, GaN-on-Si has progressed from fundamental crystal growth studies to product realization and reliability demonstration. GaN-on-Si HEMTs addressing cellular, WiMAX, and broadband RF applications are now commercially available and offer GaN performance attributes in a cost-competitive platform. This presentation will briefly describe the underlying GaN-on-Si material, process, and packaging technology, then focus primarily on performance of these products in both commercial and military applications.

All Nitronex NRF1 GaN-on-Si products are grown by MOCVD on 100 mm float-zone Si (111) substrates. A proprietary, strain-compensating (Al,Ga)N transition layer and an amorphous SixAl1-xNy nucleation layer are employed to accommodate lattice and thermal expansion mismatch between the substrate and the epilayers. The wafer fabrication process employs Ti/Al-based ohmic contacts, ion implant device isolation, 0.5 um dielectrically-defined gates, gold airbridge interconnects, and through-wafer source vias. Typical inline DC parametrics include 2DEG sheet resistance of 490 ohms/sq., on-resistance of 3 ohm-mm, peak drain current density of 830 mA/mm, and breakdown voltage of >100V. Packaging solutions include traditional LDMOS-style air cavity outlines with thermally-enhanced flange materials and low-cost plastic SOIC.

A family of devices addressing emerging OFDM-based applications such as WiMAX has been developed. WiMAX amplifiers require several watts of linear output power with frequency band allocations ranging from 2.3 to 5.8 GHz and instantaneous bandwidth up to ∼15%. Translated to the transistor level, this implies simultaneous high frequency and high voltage capability – attributes well-suited to the inherent advantages of GaN-based devices. The flagship product in this family is NPT25100, delivering 125W of peak envelope power at 2.5 GHz. Under 2.5 GHz single-carrier OFDM modulation and 10 MHz channel bandwidth, this device produces 10W linear power at 2.0% EVM with 16.5dB associated gain and 26% drain efficiency. The excellent bandwidth of NRF1 devices enables the same device to operate at cellular frequencies from 2.11 - 2.17 GHz, producing >20W average power at an adjacent channel power ratio of -35 dBc.

Primary military insertion opportunities include communications (e.g., JTRS - Joint Tactical Radio System) and electronic warfare (e.g., jammers). For EW applications, broadband operation reduces system-level component count and decreases weight / footprint. A family of 48V GaN-on-Si broadband HEMTs has been developed to deliver power levels from 40W - 180W in a compact package. In the highest power case, packaged “power density” (defined as peak output power divided by package volume) reaches ∼650 W/cm3. These power levels – in an outline suitable for highly portable systems – enable improved communications transmit distance and extend the umbrella size of electronic protection units.

We present an overview of our work concerning the fabrication of GaN-based microcavities grown on silicon substrates dedicated to the observation of the strong light-matter coupling regime. In the view of recent promising results in the field, prospects regarding the improvement of heterostructures in order to observe room temperature polariton lasing from a GaN-based microcavity grown on a silicon substrate will be discussed.