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a-Si:H TFT: Potential Suitabilities for Gate and Source-Drain Self-Aligned Structure
Published online by Cambridge University Press: 21 February 2011
Extract
Performances of a-Si:H TFT's are partly restricted by the parasitic capacitances due to the source-drain/gate overlapping and the channel length. These capacitances are inherent to the conventional photolithographic process [1] and to the MIS structure.
The use of the self-aligned a-Si:H TFT technology should allow the manufacture of short channel TFT's (L < 5 μm) where the overlapping length becomes negligible, on a large area as well as in high definition matrices. Such transistors could constitute in the near future the solution for high performances matrix arrays as well as their peripheral electronics.
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- Copyright © Materials Research Society 1984
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