A four-stage distributed amplifier utilizing low-loss slow-wave shielded (SWS) transmission lines is implemented in a standard 0.13 μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The amplifier when biased in its high current operating mode of IDtotal = 46 mA (at Vdd = 2.2 V, Pdiss = 101 mW) provides a forward transmission gain of 11.3 ± 1.5 dB with a 3-dB bandwidth of 17 GHz and a gain-bandwidth product of 74 GHz. The noise figure (NF) under the same bias condition is better than 8.5 dB up to 10 GHz. The measured output-referred 1-dB compression point is higher than +2 dBm. The amplifier is also measured under low-bias condition of IDtotal = 18 mA (at Vdd = 1.15 V, Pdiss = 20.7 mW). It provides a transmission gain of 6.6 ± 1 dB, a 3-dB bandwidth of 14.8 GHz, a gain-bandwidth product of 35.5 GHz, and a NF of better than 8.6 dB up to 10 GHz. Despite using a simple four-stage cascode design, this distributed amplifier achieves very high-gain-bandwidth product at a relatively low DC power compared to the state of the art CMOS distributed amplifiers reported in the literature. This is due to the incorporation of low-loss SWS coplanar waveguide (CPW) transmission lines with a loss factor of nearly 50% of that of standard transmission lines on CMOS-grade Si substrate.