With PLLs and ILOs introduced in Chapter 14, this chapter introduces and presents the systems that synchronize clocks to incoming data, known as clock and data recovery (CDR) systems. The chapter starts with an introduction and discussion of the metrics of CDRs. Phase detection is done differently in CDRs compared to PLLs. This is explained before the most common approaches are described. Several options are available to the designer for how phase comparisons should be acted on. These are presented and compared next. The chapter continues with an introduction to baud-rate phase detection schemes built on Mueller–Muller phase detection.

This chapter presents systems that use a voltage-controlled oscillator in a feedback loop to lock its phase to that of a reference clock. These systems, called phase-locked loops (PLLs), generate the signals used to clock decision circuits and MUX/DEMUX circuits. An introduction to PLLs and the notion of phase comparison starts this chapter. The typical Type II analog PLL is analyzed. Split tuning and details of frequency division are presented. Digital PLLs are now commonplace necessitating an overview. Injection-locked oscillators (ILOs) play an important role as clock buffers and multiphase generators This chapter gives an overview of ILO dynamics covering topics of jitter-tracking bandwidth, lock range and injection strength.