This article summarizes a unique approach in which all-ceramic interconnects are used in place of metal interconnects in solid-oxide fuel cell (SOFC) stacks. The approach combines advanced SOFC materials with the manufacturing technology and infrastructure established for multilayer ceramic (MLC) packaging for the microelectronics industry. The MLC interconnect is fabricated using multiple layers of yttria-stabilized zirconia (YSZ) tape, with each layer containing conductive vias to provide for electrical current flow through the interconnect. The all-ceramic interconnect design facilitates uniform distribution of air and fuel gas to the respective electrodes of adjacent cells. The multilayer interconnects are fabricated using traditional MLC manufacturing processes. A detailed description of the processes for fabricating the all-ceramic interconnect is presented.To aid in moving from prototype fabrication to commercialization of these fuel cell systems, a detailed cost model has been used as a roadmap for commercial stack development. Cost model projections are presented for three different interconnect footprint sizes. These projections show an SOFC stack cost of less than $150 per kilowatt for the optimized SOFC stack design produced at high volume.

Historically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.