The thermal stress behavior of silicon/quartz bonded wafer pairs is examined. Sliding, debonding, and cracking are the observed mechanisms of relaxation. When the elastic energy due to the different thermal expansion coefficients of silicon and quartz exceeds the bonding energy, sliding will start and lead to a serrated curve on the curvature-versus-temperature graph. Finally, debonding will occur once the peeling stress exceeds the interface bonding strength. The debonded parts crack due to the overhang structure, and debonding-cracking processes continue during a further temperature increase. The stress behavior of the hydrogen-implantation induced layer splitting process (the so-called “Smart-Cut process”) of silicon/quartz pairs is also monitored in a stress measurement setup. It is observed that Smart-Cut process is a sudden process in agreement with the observations reported in the literature.

We report observation of temporal decay of luminescence due to electron-hole condensation in silicon-on-insulator (SOI) wafers. The condensate luminescence was observable in SOI wafers under ultraviolet light excitation, because of shallow penetration depth of the light and confinement of photo-excited carriers in the top-Si layer. We found that the temporal decay of the luminescence depended on the surface/interface condition and fabrication method. These findings can be explained by the difference in the recombination process via surface, interface and defect states in the top-Si layer. We propose that the decay measurement of the condensate luminescence has great potential for characterization of SOI wafers.

The trend in semiconductor packaging is moving toward thinner and thinner packages. Likewise, chip profile is moving toward thinner and thinner chips. Presented here is a technique used to obtain a semiconductor package containing chips as slim as one micron in thickness. The ELO Packaging Process yields ultrathin chips for applications such as advanced heat sinking, high-efficiency optoelectronics, multiple stacked chips in a single package, and thin mechanically flexible semiconductor circuits. This technology is being developed around both the fab and packaging house so as not to interfere with the conventional semiconductor fabrication process flow.

Through a combination of back-grinding and chemical etch techniques, chips have been thinned to as little as 1 µm and bonded to a variety of new host substrates[1]. Several bonding methods have been utilized – including thin solder or epoxy layers – to bond these functional chips to a variety of new substrates. Ultrathin microwave power amplifiers have been bonded to heat sinks and optoelectronic devices have been bonded to transparent substrates. In both cases, the ultrathin chip configuration coupled with the desired substrate can increase performance of the chip by a factor of 10X.

A semi-leaky isolator composed of a magneto-optic / anisotropic waveguide was fabricated by wafer bonding technique. Characteristics of the semi-leaky isolator were investigated. The magneto-optic / anisotropic waveguide exhibited the semi-leaky characteristics. The isolation ratio of 7.2 dB/cm was obtained at a wavelength of 1.55 μm.

We report the successful fabrication of 6 µm thick slices from a ferroelectric domain micro-engineered LiNbO3 wafer device using the crystal ion slicing technique. The device was created by micropatterning ferroelectric domains in a bulk 0.3 mm thick wafer of z-cut LiNbO3, followed by ion-implanting with 3.8 MeV He+ ions to a fluence 5 × 10+16 ions/cm2 to create a damage layer at a well defined depth from the surface. Etching away this damaged layer in dilute hydrofluoric acid results in a liftoff of the top slice in which the ferroelectric domain patterns are left intact. The influence of annealing conditions on liftoff time and depth of etch lines was studied. Helium-Neon laser light was successfully coupled into the device. Due to unintentional breakage of the polished input and output faces, the electro-optic scanning performance has not been characterized so far.

Special phosphate glasses (niobium-phosphate glasses) are used for anodic bonding experiments. They are optimized particularly with regard to elevated alkali ion conductivity at room temperature due to high contents of Li or Na ions. The compounds anodically bonded at room temperature show the strength of the breakage of the glass. Only a few seconds up to a few minutes at voltages of maximum 500 V are necessary for bonding. The glasses have a thermal expansion coefficient, which is not fitted to that of silicon. Therefore, stability of the bonded compounds is achieved only at temperature jumps up to 100 K in the case of bulk samples. For higher temperature jumps the probability of breakage increases continuously. It is possible to get thin films of these glasses with ac and dc magnetron sputter techniques for example on silicon. These thin layers are anodically bondable and the compounds with silicon show a higher temperature stability (at least 233 to 473 K).

Wafer bonding and layer transfer technology has emerged as a versatile approach for integrated research and development of materials and devices. It does not only provide a flexible way to prepare integrated materials but also breaks the barrier between materials science and device engineering since it appears to be one of the fundamental technologies for 3-D device fabrication and for integration of partially or fully processed dissimilar functional layers. The device performance can be significantly enhanced when both sides of device layers can be processed such as in the double gate CMOS and in HBTs. The processed device layers can be considered as unique materials layers and can also be integrated. The integration of dissimilar integrated circuits provides a promising solution to realize micro-systems or system on a 3-D chip in which multi-functional layers are interconnected (3-D SOC). The main issues are to develop methods that form strong bond between required materials at low temperatures and to cut the device layer without compromising the device integrity by using VLSI compatible processes. The advances in low temperature bonding of hydrophilic and hydrophobic silicon, compound semiconductors and other materials in ambient are reviewed, and application examples are discussed.

Proton implantation and thermal annealing of silicon result in the formation of a specific type of extended defect involving hydrogen, named “platelets”. These defects have been related to the exfoliation mechanism on which a newly developed process to transfer thin films of silicon onto various substrates is based. In a previous paper, we have shown that these platelets undergo a quasi-conservative Ostwald ripening upon annealing. The measurement of the pressure within such pressurised gas-filled cavities is important to understand and simulate both the growth of these defects and the exfoliation mechanism. To extract this pressure from TEM studies, we have developed and tested an analogy between the platelets and a well-known 2D defect: a dislocation loop. The comparison between simulations of the image of the strain field surrounding a fictitious dislocation loop and experimental TEM images of the platelets shows that the platelets can be described by a Burgers vector of about 0.6nm. Moreover, this vector can be used to deduce the pressure of the molecular hydrogen within a platelet. A typical value of 10 GPa is found for a platelet of 20 nm in diameter at room temperature. Consequently, the atomic density of hydrogen within a platelet and the total number of hydrogen trapped by a population of platelet can be calculated and give reasonable values when compared to the implanted dose.

An innovative suite of layer transfer technologies, collectively called the NanoCleaveTM Process, includes a non-porous cleave plane utilizing a compressive strain layer, growth of a high purity, crystalline device layer, plasma activation coupled with vacuum bonding, room-temperature cleaving along an atomically flat plane and a variety of post-cleave CVD processes to thicken or thin the device layer to a desired final thickness is described. Applications of this process include fabrication of SOI wafers containing Si and SiGe alloy device layers.