The effects of light saturation on the properties of undoped a-Si:H films were studied by a new capacitance profiling technique which can be used to directly determine changes in the dangling bond density of states near midgap. Coplanar conductivity and capacitance vs. temperature measurements save the changes in activation energies for electrical conductivity. These studies indicate that, while substantial increases in the dangling bond densities are observed for most samples, the detailed behavior of the light induced changes in these films are inconsistent with the creation of such defects by breaking weak valence band tail states.

Boron-doping the i-layer in p-i-n amorphous silicon solar cells improves the device performance when the density of impurities in the undoped i-layer material is high (< 1020 cm-3). While this technique can boost the initial device efficiencies for poor quality i-layer material, our devices degrade faster than devices made with undoped, low impurity i-layer material. We have measured the degradation of photovoltaic parameters as a function of continuous AM1 exposure time for devices with and without B-doped i-layers. For single junction p-i-n solar cells with comparable initial conversion efficiencies (< 7%, area < 1cm2) we find that our devices containing i-layers deposited from gas mixtures containing 2–3 ppm diborane degrade faster than devices containing undoped i-layers. Similar effects are observed when two-junction stacked cells with B-doped i-layers are compared to two-junction stacked cells with undoped i-layers.

pin cells with the light entering the n-layer (pinITO) or the p-layer (SnO2p(C)in) were prepared taking into account the ‘basic’ boron profile in the i-layer. Their efficiencies (up to 7.4% and 10.1%) show a light-induced degradation. This can be removed by doping the i-layer of pinITO cells with a decreasing boron profile. The initial efficiency is only slightly affected. Cells containing fluorine due to prior plasma-etching require higher amounts of boron for stability. For the cell type SnO2p(C)in, phosphorus profiles, however increasing towards the n-layer, lead to reduced cell degradation without affecting the efficiency. The results of profiling were interpreted in terms of a recombination model.

The light-induced performance degradation of amorphous silicon solar cells is described well by a model in which the carrier lifetimes are determined by the dangling bond density. The kinetics of the defect generation follow the model in which band-to-band recombination provides the energy for the creation of dangling bonds, which in turn introduce gap states that reduce carrier lifetime. Degradation will be slower in solar cells operating at lower excess carrier concentrations. This is documented with a comparison of degradation data for cells of different i-layer thickness, cells operating at open circuit vs. load, and for single vs. cascade cells. The model also correctly predicts the relation between short circuit current and fill factor degradation. At sufficiently long times, the efficiency will decrease at approximately the same rate for all cell structures and dimensions, with an offset in time between different device types which can be calculated.

The preparation of amorphous silicon with a low density of defect states by the glow discharge decomposition of silane and the ability to control its electrical conductivity over many orders of magnitude by the addition of phosphine or diborane to the silane, stimulated a worldwide interest in this material and in its possible applications. This paper begins with a description of the preparation technique and a brief review of some of the important properties of the material. The fabrication and characteristics of a-Si thin-film field effect transistors will be described and followed by a discussion of the applications of these devices in large area liquid crystal displays, in simple logic circuits and in addressable image sensors. Finally, the use of a-Si in memory devices will be briefly described.

We report improvements in device structures by the reduction of capacitance in short channel length thin film transistors of amorphous silicon alloy materials. Employing techniques similar to those previously reported [1,2], these MOS structures are fabricated with channel lengths of 1 to 2 micrometers using standard photolithography with 10 micrometer minimum feature size. Significant reductions in capacitance over earlier reported device designs were achieved by improvements in device geometry and innovative use of shadowing techniques utilizing oblique angle deposition to minimize overlap between electrodes. Theses reduced capacitance short channel length TFTs enhance the possibility of fabricating on-board drivers for active matrix liquid crystal displays using amorphous silicon alloy devices. Despite the relatively low mobility of amorphous silicon (∼ 1 cm2 /V-sec) these short channel length TFTs can provide currents large enough for operation in the megahertz regime when these reductions in capacitance are incorporated. The noncritical photolithography assures that devices may be fabricated over large area substrates (8" × 8") with acceptable yields. Computer simulations predict that these TFTs will be able to provide the necessary speed for on-substrate drivers. We will present experimental results from the new TFT structures and describe modeling methods and results for amorphous silicon TFT ring oscillators. We will discuss the significance of these results as they pertain to drive circuitry for large area liquid crystal displays.

The characteristics of a thin-film transistor using an amorphous-silicon film are presented. The appearance of electron and hole channels is made possible by ohmic source and drain contacts. A theoretical model explains the phenomena.

Prototype thin film transistors have previously been fabricated by r.f. magnetron sputtering of a-Si:H on to CVD Si02 using a crystalline silicon gate. These devices exhibited an on/off current ratio of four orders of magnitude for gate voltages as low as 10 volts. This demonstrated the suitability of the sputtered layer for liquid crystal display applications.

The use of a crystalline substrate negates the advantages of using a thin film,such as large area capability and low cost, so we have turned our attention to the provision of a sputtered dielectric. Several candidate materials have been considered, including Si02, Si3N4, Ta205, AIN and Ti02. We present the characteristics of our first all-sputtered transistor utilising an Si02 gate,and assess the dielectric properties and potential of other materials, with emphasis on the silicon oxynitride system.

Experimental studies on the above threshold characteristics of amorphous silicon alloy thin films transistors show that the field-effect mobility has a weak temperature dependence and that the current-voltage characteristics are described by a power law dependence on gate voltage, with an exponent greater than two. These results are in good agreement with our theoretical model, which demonstrates that in the above threshold regime, the Fermi level at the semiconductor-insulator interface lies in the tail states which control device performance. Analysis of the above threshold characteristics shows the characteristic energy variation of the exponential tail state distribution to be ∼22meV and that the on current changes by a factor of only two over the temperature range lO−90°C.

A novel dynamic circuit composed of amorphous-silicon Schottkybarrier diodes and field-effect transistors has been proposed. The circuit response time is as short as the discharging time of a load capacitor through the driver transistor. The circuit having 1µm-long, self-aligned transistors has been predicted theoretically to be able to be operated at multi-MHz rates. Preliminary experimental results are also presented.

A 32×32 pixel liquid crystal display using amorphous silicon n-i-n diodes as switching elements has been developed. The display can be operated at duty ratios up to 1:256.

We report on measurements of conduction, threshold switching and high frecuency oscillations (∼100 MHZ) on amorphous silicon prgduced by RF sputtering in lateral devices with a very small (4µm2 to 40µm2 ) metalic contact area. The results show that the mechanism of threshold switching in this material is not due to the formation of a metalic filament through diffusion of the contacts. A small amount of Hydrogen (PH2/PAr=0.025) is sufficient to inhibit threshold switching. The “Zero voltage” resistance is reproducible and seems to be independent of the switching events.

The history in developing a-Si image devices, photoreceptor and vidicon is briefly reviewed. Some problems to be solved are discussed for the device structures and preparation techniques of Si-base alloys and Si itself from technical point of view.

A new multilayer amorphous silicon alloy photoreceptor has been deposited at rates exceeding 36 µm/hr. using 2.45 GHz microwave glow discharge. The device whose structure is Al/a-Si:H:F (B-300)/a-Si:H:F (B-10)/a-Si:H:F:C is deposited in a powderless plasma deposition process which exhibits gas utilization efficiency approaching 100%. The xerographic performance of a 28µm device is: Vsat∼1100 V for a +7 KV corona; dark half decay time ≃5 sec; and photosensitivity ∼0.3 µJ/cm2 at λ = 650 nm. Stable, high quality xerographic images are obtained with these photoreceptors.

The effects of characteristics of the blocking layers in multilayered a-Si:H photoreceptors on electrophotographic properties are reported. The structure of the photoreceptor is Al/a-Si:H(p)/a-Si:H(i)/a-Si1−xCx. The thickness and boron doping ratio of the bottom p-type layer and the thickness and compositional fraction x of the surface a-Si1−xCx layer are varied. It is shown that the dark decay time is particularly sensitive to the thickness and doping ratio of the p-type layer. These dependences are discussed assuming a space charge layer in the p-type layer. It is also shown that the thickness and x of the a-Si1−xCx layer greatly influence the residual voltage and effective quantum efficiency of photocarrier generation.

Document width linear image sensor arouse strong and wide interest as a compact image reading component for facsimile and other document readers. Among those, a-Si:H is excellent in stability and light sensitivity. The photosensing element of those sensors have a sandwich-like structure which consist of Cr/i-a-Si:H/ITO. In this structure, i-a-Si:H/ITO shows good shottky contact resulting high photo to dark current ratio and fast photoresponse. We have been developing linear image sensor of A4 and B4 size with resolutions of 8dot/mm and l6dot/mm and had applied successfully to facsimile and image input terminals.

This paper reports heterojunction photodiode properties and its application to a compact scanner. The photodiode has ITO / p-a-SiC:H / a-Si:H / metal structure. This diode has high photo to dark current ratio and small photocurrent saturation voltage, because of the excellent blocking characteristics for a heterojunction with large built in potential. Moreover, a-Si:H / metal contact has been investigated. A contact linear image sensor has been fabricated using the heterojunction photodiode array and compact optical system. Performance tests showed excellent results. Good reproduced images have been obtained.

The short response times required for image sensors demand blocking contacts at the sensor cell. It was found that the junctions between transparent electrodes (ITO or a thin palladium film) and the metallic back electrode with a-Si:H form blocking contacts yielding photocurrent decay times of the order of some microseconds. The two different time regimes observed for the decay are interpreted as being limited by the drift and the release of holes respectively.

For the first time an operating heterojunction bipolar silicon transistor has been realized with phosphorous doped amorphous silicon (a-Si) emitter. The deposition of a-Si is a relatively simple technique. The current gain (β) of 14 at a base Gummel Number (G.N.) of 1.35 1013 s/cm4 is higher than that obtained with normal diffused emitter bipolar transistors with the same G.N. for the base. This adds a degree of freedom to the design of bipolar structures according to the compromise between base resistance and current gainCrucial points that have to be looked at further are interface recombination at the a-Si/c-Si transition and emitter resistance.

The goal of this work was to produce a fabrication process for high performance polycrystalline silicon thin film MOS devices. We have fabricated p-channel devices with mobilities of 35 cm2/V-sec and n-channel devices with mobilities of 50 cm2/V-sec by tailoring the process for depositon of the channel layer, by gate oxidation of the channel at high temperature, and by use of plasma hydrogenation. Under optimal conditions deduced from the study, device threshold voltages are close to zero. Leakage currents in the off-state are less than 0.1 pA/µm of channel length. Fabrication of the devices requires four mask levels and employs standard process steps. Therefore, polycrystalline silicon devices are attractive candidates for a variety of electronics applications, including thin film logic over large area.