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Designing Ultra Low-k Dielectric Materials for Ease of Patterning

Published online by Cambridge University Press:  01 February 2011

George Andrew Antonelli
Affiliation:
[email protected], Novellus Systems, Inc., External Research & Development, Albany, New York, United States
Gengwei Jiang
Affiliation:
[email protected], Novellus Systems, Inc., PECVD Business Unit, Tualatin, Oregon, United States
Mandyam Sriram
Affiliation:
[email protected], Novellus Systems, Inc., PECVD Business Unit, Tualatin, Oregon, United States
Kaushik Chattopadhyay
Affiliation:
[email protected], Novellus Systems, Inc., Customer Integration Center, San Jose, California, United States
Wei Guo
Affiliation:
[email protected], Massachusetts Institute of Technology, Chemical Engineering, Cambridge, Massachusetts, United States
Herbert Sawin
Affiliation:
[email protected], Massachusetts Institute of Technology, Chemical Engineering, Cambridge, Massachusetts, United States
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Abstract

Organosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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