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Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

Published online by Cambridge University Press:  05 June 2014

Sami Ghedira ,
Cyril Buttay ,
Hervé Morel  and
Kamel Besbes
Sami Ghedira*
Affiliation:
University of Monastir, Micro-electronics and Instrumentation Laboratory, Environment Boulevard, 5019 Monastir, Tunisia
Cyril Buttay
Affiliation:
Institut National des Sciences Appliquées de Lyon (INSA-Lyon), Laboratoire Ampére, UMR 5005, 69621 Villeurbanne, France
Hervé Morel
Affiliation:
Institut National des Sciences Appliquées de Lyon (INSA-Lyon), Laboratoire Ampére, UMR 5005, 69621 Villeurbanne, France
Kamel Besbes
Affiliation:
University of Monastir, Micro-electronics and Instrumentation Laboratory, Environment Boulevard, 5019 Monastir, Tunisia
*
ae-mail: [email protected]
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Abstract

In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors CGS, CDS and CGD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance CGD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of CGD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 66 , Issue 2 , May 2014 , 20103
Copyright
© EDP Sciences, 2014

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