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Through Wafer Interconnects for 3-D Packaging

Published online by Cambridge University Press:  26 February 2011

Amy J. Moll
Affiliation:
[email protected], Boise State University, Materials Science & Engineering, 1910 Univ Dr, Boise, ID, 83725-2075, United States, 208-426-5719
William B. Knowlton
Affiliation:
[email protected], Boise State University, Materials Science & Engineering, Boise, ID, 83725-2075, United States
Rex Oxford
Affiliation:
[email protected], Boise State University, Materials Science & Engineering, Boise, ID, 83725-2075, United States
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Abstract

Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

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