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Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

Published online by Cambridge University Press:  31 January 2011

Yasaman Shadrokh ,
Kristel Fobelets  and
Enrique Velazquez-Perez
Yasaman Shadrokh
Affiliation:
[email protected], Imperial College, Electronic and Electrical Engineering, London, United Kingdom
Kristel Fobelets
Affiliation:
[email protected], Imperial College, Electronic and Electrical Engineering, London, United Kingdom
Enrique Velazquez-Perez
Affiliation:
[email protected], Universidad de Salamanca, Departmento de Física Aplicada, Salamanca, Spain
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Abstract

Reduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

Keywords

electrical propertiesnanostructuresimulation
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1174: Symposium V – Functional Metal-Oxide Nanostructures , 2009 , 1174-V09-36
Copyright
Copyright © Materials Research Society 2009

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References

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