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Metallization for Very-Large-Scale Integrated Circuits

Published online by Cambridge University Press:  15 February 2011

P. B. Ghate
P. B. Ghate*
Affiliation:
Semiconductor Research and Development Laboratories, Texas Instruments Inc., Dallas, TX 75265 (U.S.A.)
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Abstract

Progress in patterning technologies and computer-aided circuit designs have brought us to the threshold of very-large-scale integrated (VLSI) circuits with 100 000 or more devices to be integrated on a silicon chip. In this paper we review thin film applications in the fabrication of contacts and interconnects for VLSI circuits. Device structures suitable for both bipolar and metal/oxide/semiconductor (MOS) VLSI circuit applications tend to have shallow junction depths and contact areas (silicon-metal interfaces) in the 0.2–0.5 μm and 1–2μm2 ranges respectively; also some of the circuits require Schottky barrier diodes. Consumption of silicon in the contact windows needs to be minimized with the use of silicide layers for siliconmetal contacts. The formation and use of platinum silicide layers for bipolar applications are reviewed. Our observations indicate that the carbon and oxygen present in Czochralski-grown silicon crystals interfere in platinum silicide formationand affect the electrical characteristics of the contacts. The use of barrier layers in VLSI metallization is illustrated. The interdependence of film microstructure, electromigration-induced failures and VLSI interconnection reliability is examined. The integration of a large number of components on a VLSI chip with a single level of interconnections consumes more chip area. Long interconnection paths adversely affect circuit performance. Multilevel interconnections (conductor/insulator/conductor) offer an attractive solution to increase the packing density and circuit performance. The application of PtSi/(Ti: W)/(Al-Cu)/SiO2 /(Ti: W)/A1 film layers in the fabrication of a bipolar VLSI circuit with a minimum feature size of 1.25 μm is illustrated. As the complexity of VLSI circuits continues to grow with micron size device structures, three or more levels of interconnections compatible with shallow junctions on the substrates and complex packaging technologies are required. Areas of concern and desirable features in VLSI metallization are summarized.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 10: Symposium C – Thin Films and Interfaces I , 1981 , 371
Copyright
Copyright © Materials Research Society 1982

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