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High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors

Published online by Cambridge University Press:  14 March 2011

N. Tosic ,
F. G. Kuper  and
T. Mouthaan
N. Tosic
Affiliation:
University of Twente, MESA+ Institute, P.O. Box 217, 7500 AE Enschede, The, Netherlands
F. G. Kuper
Affiliation:
University of Twente, MESA+ Institute, P.O. Box 217, 7500 AE Enschede, The, Netherlands Philips Semiconductors, MOS4YOU, Nijmegen, The, Netherlands
T. Mouthaan
Affiliation:
University of Twente, MESA+ Institute, P.O. Box 217, 7500 AE Enschede, The, Netherlands
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Abstract

In this paper, an analysis of the high voltage induced degradation in top gate amorphous silicon Thin Film Transistors (TFT) will be shown, including the aspect of self-heating. It will be shown through experimental results that the degradation level under high voltages on drain and gate is different for TFT's with different channel lengths. In addition, the temperature distribution over the TFT area for devices with different channel length is simulated. Simulation shows that the peak of temperature distribution is located at the drain/channel edge and that level of thermal heating depends on the channel length.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 621: Symposia Q/R – Electron-Emissive Materials, Vacuum Microelectronics… , 2000 , Q8.5.1
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

1. Tosic, N., Kuper, F.G., Mouthaan, T., “Transmission line model testing of top-gate amorphous silicon thin-film transistors”, Proc. of IRPS 2000 Conference.Google Scholar
2. Tada, M., Uchikoga, S., Ikeda, M., “Power-density-dependent failure of amorphous Si TFT”, Proc. of AM-LCD '96, pp. 269–272.Google Scholar