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Degradation in a Molybdenum-Gate MOS Structure Caused by N+ Ion Implantation for Work Function Control

Published online by Cambridge University Press:  01 February 2011

Takaaki Amada ,
Nobuhide Maeda  and
Kentaro Shibahara
Takaaki Amada
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2, Kagamiyama, Higashihiroshima, Hiroshima, 739-8527 Japan.
Nobuhide Maeda
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2, Kagamiyama, Higashihiroshima, Hiroshima, 739-8527 Japan.
Kentaro Shibahara
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2, Kagamiyama, Higashihiroshima, Hiroshima, 739-8527 Japan.
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Abstract

An Mo gate work function control technique which uses annealing or N+ ion implantation has been reported by Ranade et al. We have fabricated Mo-gate MOS diodes, based on their report, with 5-20 nm SiO2 and found that the gate leakage current was increased as the N+ implantation dose and implantation energy were increased. Although a work function shift was observed in the C-V characteristics, a hump caused by high-density interface states was found for high-dose specimens. Nevertheless, a work function shift larger than -1V was achieved. However, nitrogen concentration at the Si surface was about 1x1020 cm-3 for the specimen with a large work function shift.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 716: Symposium B – Silicon Materials-Processing, Characterization, and Reliability , 2002 , B7.5
Copyright
Copyright © Materials Research Society 2002

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References

1.International Technology Roadmap for Semiconductors, Process Integration & Device Structure (2001).Google Scholar
2. Chatterjee, A., Chapman, R.A., Joyner, K., Otobe, M., Hattangady, S. et al., Technical Digest of IEEE Int. Electron Devices Meeting, (1998) pp. 777–780.Google Scholar
3. Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Matsuo, K., Shibata, T., Tsunashima, Y., Suguro, K., and Arikado, T., IEEE Trans. Electron Devices, 48, 8 (2001) pp. 1604–1611.Google Scholar
4. Ranade, P., Yeo, Y. C., Lu, Q., Takeuchi, H., King, T. J., Hu, C., Symposium Proceedings, Mat. Res. Soc. Proc., 611 (2001) pp. C3.2–C3.2.6.Google Scholar
5. Lu, Qiang, Yeo, Y. C., Ranade, P., Takeuchi, H., King, T. J., Digest of Symp. on VLSI Tech., (2001) pp. 45–46.Google Scholar
6. Ranade, P., Lin, R., Lu, Q., Yeo, Y. C., Takeuchi, H., King, T. J., Hu, C., Symposium, Mat. Res. Soc. Proc., 670 (2001) pp. K5.2–K5.2.6.Google Scholar
7.http://www.srim.org/Google Scholar
8. Pavlov, P. V., Zorin, E. I., Tetelbaum, D. I., and Khokhlov, A. F., Physica Status Solidi, (A) 35, 11 (1976) pp. 12–36.Google Scholar