Hostname: page-component-78c5997874-m6dg7 Total loading time: 0 Render date: 2024-11-18T12:19:10.095Z Has data issue: false hasContentIssue false
  • English
  • Français

The Positive Gate Bias Annealing Method for the Suppression of a Leakage Current in the SPC-Si TFT on a Glass Substrate

Published online by Cambridge University Press:  01 February 2011

Sang-Geun Park ,
Joong-Hyun Park ,
Seung-Hee Kuk ,
Dong-Won Kang  and
Min-Koo Han
Sang-Geun Park
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Joong-Hyun Park
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Seung-Hee Kuk
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Dong-Won Kang
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Min-Koo Han
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Get access

Abstract

We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=−20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

Keywords

displaySithin film
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1066: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology—2008 , 2008 , 1066-A13-03
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Powell, M.J., “Charge trapping instabilities in amorphous silicon-silicon nitride thin-film transistors”, Appl. Phys. Lett. 43(6), pp.597–599, 1983.Google Scholar
2. Farmakis, F. V., Brini, J. Kamarinos, G. Angelis, C. T., Dimitriadis, C. A., and Miyasaka, M. “On-Current Modeling of Large-Grain Polycrystalline Silicon Thin-Film Transistors”, Ieee Transactions on Electron Devices, VOL. 48, No. 4, Apr. 2001 Google Scholar
3. Lee, J.H, Park, H.S, Jeon, J.H, and Han, M.K, “Suppression of TFT leakage current effect on active matrix displays by employing a new circular switch”, Solid-State Electronics, vol.52, Issue 3. pp.467–472, Mar., 2008.Google Scholar
4. Kail, F. Hadjadj, A. Cabarrocas, P. Rocai, “Hydrogen diffusion and induced-crystallization in intrinsic and doped hydrogenated amorphous silicon films”, Thin Solid Films, vol. 487, Issues 1-2, 1 pp. 126–131, Sep, 2005 Google Scholar
5. Yazakis, M. Takenakal, S. and Ohshima, H. “Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors”, Jpn. J. Appl. Phys. Vol. 31 pp.206–209 Part 1, No. 2A, 15 Feb., 1992 Google Scholar
6. Moon, K.C, Lee, J.H, and Han, M.K, “The Study of Hot-Carrier Stress on Poly-Si TFT Employing C-V Measurement”, IEEE Transaction on Electron Device, vol.52, No.4, pp.512–517, April, 2005 Google Scholar